Description of the Casio NM-320 / uPD1007 microprocessor assembly language

Most mnemonic names were adopted from the Casio's HD61700 official instruction
set.


The symbols listed below are used in the explanations and examples throughout
this document:

Rf..Rl		array of data registers
Im6		6-bit immediate data &H00..&H3F
Im8		8-bit immediate data &H00..&HFF
Im16		16-bit immediate data &H0000..&HFFFF
<-		Transfer direction
&H		Prefix of a hexadecimal literal
( )		Contents of memory pointed to by the register included within
		parentheses



Internal registers
==================

The internal RAM is organized as 128 general purpose 8-bit registers divided
into two 64-byte banks RB0..RB1 and sixteen 8-byte pages RP0..RP15:

RB0 - registers R0..R63

RP0 - registers R0..R7
RP1 - registers R8..R15
RP2 - registers R16..R23
RP3 - registers R24..R31
RP4 - registers R32..R39
RP5 - registers R40..R47
RP6 - registers R48..R55
RP7 - registers R56..R63

RB1 - registers R64..R127

RP8 - registers R64..R71
RP9 - registers R72..R79
RP10 - registers R80..R87
RP11 - registers R88..R95
RP12 - registers R96..R103
RP13 - registers R104..R111
RP14 - registers R112..R119
RP15 - registers R120..R127

Up to 8 adjacent registers within the same page can be combined to handle up
to 64-bit data. The little-endian byte order is used (the least significant
first).

The registers in the bank RB1 can be accessed not only directly through their
absolute address, but also indirectly through the contents of the AS register.
Depending on the bit 0 of the AS register, only the lower 3 or all 6 bits of
the directly specified register address (index) are replaced with the contents
of the AS register.

Register notation:

 1. directly specified registers - letter 'R' followed by a decimal number in
  range 0..127

 2. indirectly specified registers (where part of the address is modified by
  the contents of the AS register) - letter 'I' followed by a decimal number
  in range 64..127

Registers R120..R127 (most significant byte) and R56..R63 (least significand
byte) form 8 special purpose 16-bit registers:
R120,R56 - index register IX
R121,R57 - index register IY
R122,R58 - index register IZ
R123,R59 - trap vector V3
R124,R60 - interrupt vector V2, address of the INT2 service routine
R125,R61 - interrupt vector V1, address of the INT1 service routine
R126,R62 - interrupt vector V0, address of the INT0 service routine
R127,R63 - hardware stack pointer SP


F: Flag Register (8-bit, Read/Write)

	MSB     ->     LSB
	C H V NZ UZ LZ * *

bit 7 - Carry Flag C, set to 1 when a carry or borrow occurs from bit 7 to
 bit 8 (C), and reset to 0 when a carry or borrow from bit 7 to bit 8 does
 not occur (NC).
bit 6 - Half Carry Flag H, set to 1 when a carry or borrow occurs from bit 3
 to bit 4 (H), and reset to 0 when a carry or borrow from bit 3 to bit 4 does
 not occur (NH).
bit 5 - Overflow Flag V, set to 1 when a carry or borrow occurs from bit 6
 to bit 7 (V), and reset to 0 when a carry or borrow from bit 6 to bit 7
 does not occur (NV). It can be used along with the Carry Flag to detect
 a two's-complement overflow condition as a result of an addition or
 a subtraction. The result of the operation is invalid when the V bit is set
 and the C bit is reset, or else when the V bit is reset and the C bit is set.
bit 4 - Not Zero Flag NZ, reset to 0 when all the bits of a calculation result
 are 0 (Z), and set to 1 when data are present (NZ).
bit 3 - Upper Digit Zero Flag UZ, set to 1 when the high-order 4 bits are 0
 due to a calculation result (UZ), and reset to 0 when data are present (NUZ).
bit 2 - Lower Digit Zero Flag LZ, set to 1 when the low-order 4 bits are 0
 due to a calculation result (LZ), and reset to 0 when data are present (NLZ).

In case of multibyte instructions the flags are set by the last processed
byte, except for the Not Zero Flag which is cleared only when all bytes are 0.


KO: Keyboard Output Port Register (8-bit register, Read/Write)

- when read, returns the written value

- when written, selects lines of the 12-bit KO output port

	KO12 - 1x1xxxxx		;x denote "don't care"
	KO11 - 1xx1xxxx
	KO10 - 1xxx1xxx
	KO9  - 1xxxx1xx
	KO8  - 1xxxxx1x
	KO7  - 1xxxxxx1
	KO6  - x11xxxxx
	KO5  - x1x1xxxx
	KO4  - x1xx1xxx
	KO3  - x1xxx1xx
	KO2  - x1xxxx1x
	KO1  - x1xxxxx1


KI: Keyboard Input Port Register (8-bit, Read only) - returns the state of
 the keyboard input port when the bit 7 or bit 6 of the KO register is set,
 otherwise retains the last captured value.
 The contents of the KI register can be tested against zero with the
 conditional jump/call on K/NK. Note that the K/NK condition doesn't have
 any corresponding bit in the Flag Register.
 Example:
	    PST KO,&H42	;select the key output KO2
	L1: JMP NK,L1	;wait for a key to be pressed
	    PST KO,&H00	;latch the keyboard input port state
	    GST R1,KI	;read the captured keyboard input port state


IE: Interrupt Enable Register (8-bit, Read/Write)

bit 7 - slow mode or external clock enable

bit 6 - INT2 interrupt enable
bit 5 - INT1 interrupt enable
bit 4 - INT0 interrupt enable

bit 2 - system clock options, enabled when bit 7 is set
	0: slow mode - the system clock is divided by 2
	1: ext. clock - signal on the INT1 input is used as the system clock

The INT0 has the highest priority level, the INT2 has the lowest priority
level. The INTx inputs are falling edge sensitive.
An interrupt service routine of lower priority can be always interrupted by
a higher priority interrupt.

bits 1,0 - select memory bank for data access
	00 - asserts the FE output
	01 - asserts the CS1 output
	10 - asserts the CS2 output
	11 - asserts the CS3 output

When the instructions are fetched or the return address is transferred to/from
the stack, then always bank 00 is accessed, regardless of the IE contents.


IF: Interrupt Flags (8-bit, the bits 4 and 0 can be read and written,
 the other ones are read only)
bit 7 - INT2 interrupt service flag
bit 6 - INT1 interrupt service flag
bit 5 - INT0 interrupt service flag
bit 4 - controls or returns the state of the EN2 output (set if low level)
bit 3 - state of the INT2 input (set if low level)
bit 2 - state of the INT1 input (set if low level)
bit 1 - state of the INT0 input (set if low level)
bit 0 - controls or returns the state of the EN1 output (set if low level)

Bits 7..5 are set by hardware when an interrupt is being serviced (not upon an
interrupt request!), and cleared either by the RTI instruction, or by the CANI
instruction, or by disabling the corresponding interrupt.


AS: Address Select (8-bit, Read/Write) - modifier of the register address
 allowing indirect access to the general purpose registers in the bank RB1.
 Order of bits: *543210M (M=mode)

 Indirect addressing to the register arrays is also possible. The indirectly
 specified array doesn't need to be aligned with the other one.

Options:

 1. When the bit 0 of the AS register is cleared, bits 6..1 form the address
  of the indirectly specified register in range R64..R127. The direct register
  address specified by the instruction opcode is ignored.
  bits: 0RRRRRR0

  Example how to clear registers R64 to R111 using indirect addressing
	    LD  R50,&H00
	    LD  R12,&H5E	;initialise the pointer to the register R111
	L1: PST AS,R12		;set the pointer
	    LD  I64,R50		;write R50 to the register pointed to by AS
	    SB  R12,&H02	;decrement the pointer
	    JMP NC,L1

  In this mode an indirectly specified array cannot wrap around. Reading an
  indirectly adressed register outside the page boundaries returns 0, writing
  has no effect.

  Examples:

  1.1 instruction LDM R2..R5,I106..I109

  AS=&H12: R2<-R73 R3<-R74 R4<-R75 R5<-R76	;the arrays don't need to be
						;aligned
  AS=&H1C: R2<-R78 R3<-R79 R4<-&H00 R5<-&H00	;crossed page boundary

  1.2 instruction DIUM I104..I107

  AS=&H26 - processed registers: R83, R84, R85, R86, because the page boundary
   wasn't crossed
  AS=&H2A - processed registers: R85, R86, R87 and a dummy virtual register
   outside the page boundary containing &H00

  1.3 instruction DIDM I107..I104

  AS=&H4C - processed registers: R102, R101, R100, R99, because the page
   boundary wasn't crossed
  AS=&H44 - processed registers: R98, R97, R96 and a dummy virtual register
   outside the page boundary, containing &H00

 2. When the bit 0 of the AS register is set, only bits 3..1 thereof modify
  the bits 2..0 of the address of the indirectly specified register. The bits
  5..3 of the address remain as set by the instruction opcode.
  bits: 0xxxRRR1 (x=ignored)

  Example:
	    PST AS,&H07
	    LD  R5,I104		;the contents of the register R107 will be
				;transferred to the register R5

  In case of an indirectly specified array, bits 3..1 specify the first
  register of the array, while bits 6..4 specify the last register of the
  array. For instructions which process registers downwards (BYDM, DIDM, RODM)
  the bits 6..4 are inverted.
  Reading an indirectly addressed register after the last one returns 0,
  writing has no effect.
  bits: 0LLLFFF1

  Examples:

  2.1 instruction LDM R2..R5,I106..I109

  AS=&H77: R2<-R107 R3<-R108 R4<-R109 R5<-R110	;last indirectly specified
						;register = R111, the arrays
						;don't need to be aligned
  AS=&H47: R2<-R107 R3<-R108 R4<-&H00 R5<-&H00	;last indirectly specified
						;register = R108
  AS=&H5D: R2<-R110 R3<-R111 R4<-R104 R5<-R105	;last indirectly specified
						;register = R109, wrapping
						;around is supported

  2.2 instruction LDM I106..I109,R2..R5

  AS=&H47: R107<-R2 R108<-R3 void<-R4 void<-R5	;last indirectly specified
						;register = R108

  2.3 instruction DIUM I104..I107

  AS=&H75 - processed registers: R106, R107, R108, R109, last indirectly
   specified register = R111
  AS=&H45 - processed registers: R106, R107, R108 and a dummy virtual register
   containing &H00, because R108 was indirectly specified as the last one
  AS=&H5D - processed registers: R110, R111, R104, R105, last indirectly
   specified register = R109, wrapping around is supported

  2.4 instruction DIDM I107..I104

  AS=&H79 - processed registers: R108, R107, R106, R105, last indirectly
   specified register = R104
  AS=&H59 - processed registers: R108, R107, R106 and a dummy virtual register
   containing &H00, because R106 was indirectly specified as the last one
  AS=&H53 - processed registers: R105, R104, R111, R110, last indirectly
   specified register = R106, wrapping around is supported


Display Driver Control Register (Write only, 6-bit), outputs a control signal
when commands or display data are sent to the display driver.

bit 5 - OP (operation, set when command, cleared when data)
bit 4
bit 3
bit 2 - CE3 (unused in the FX-8000G)
bit 1 - CE2 (unused in the FX-8000G)
bit 0 - CE1 (chip enable signal for the LCD driver in the FX-8000G)



Instruction syntax
==================

Example mnemonic name: TADBM
T - test mode, the result of operation isn't stored
AD - addition
B - decimal mode (BCD)
M - multibyte

Order of operands: destination, source



Instruction set
===============

Mnemonic:	AD (Add)
Syntax:		AD dst,src
Execution:	dst <- dst + src
Description:	Adds the source to the destination and stores the result in
		the destination.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		AD Rd,Rs	;the source and destination register must
				;belong to different register banks
		AD Rd,Im8
Examples:
		AD R10,R70
		AD R80,R20
		AD R25,I88
		AD I99,R44
		AD R16,&H55

--------------------

Mnemonic:	ADB (Add BCD)
Syntax:		ADB dst,src
Execution:	dst <- dst + src, produces a decimal result
Description:	Adds the source to the destination, and stores the result in
		the destination. Each byte is assumed to contain two digits
		in binary-coded decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		ADB Rd,Rs	;the source and destination register must
				;belong to different register banks
		ADB Rd,Im8
Examples:
		ADB R10,R70
		ADB R80,R20
		ADB R25,I88
		ADB I99,R44
		ADB R16,&H55

--------------------

Mnemonic:	ADBM (Add BCD Multibyte)
Syntax:		ADBM dst,src
Execution:	dst <- dst + src, produces a decimal result
Description:	Adds the source to the destination array, and stores the
		result in the destination array. Each byte is assumed to
		contain two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		ADBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		ADBM R0..R3,R64..R67
		ADBM R73..R76,&H25
		ADBM R24..R31,I96..I103
		ADBM I66..I67,R58..R59

--------------------

Mnemonic:	ADM (Add Multibyte)
Syntax:		ADM dst,src
Execution:	dst <- dst + src
Description:	Adds the source to the destination array and stores the result
		in the destination array.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		ADM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		ADM R100..R103,R44..R47
		ADM R24..R31,&H1C
		ADM R24..R31,I96..I103
		ADM I76..I79,R44..R47

--------------------

Mnemonic:	ADW (Add Word)
Syntax:		ADW dst,Im8
Execution:	dst <- dst + Im8
Description:	Adds the 8-bit immediate data to the 16-bit index register
		and stores the result in the index register.
Flags:		none affected
Options:
		ADW IX,Im8
		ADW IY,Im8
		ADW IZ,Im8
		ADW SP,Im8
Examples:
		ADW IX,&H5A		;IX <- IX + &H5A
		ADW SP,&HF0		;SP <- SP + &HF0

--------------------

Mnemonic:	AN (Logical AND)
Syntax:		AN dst,src
Execution:	dst <- dst AND src
Description:	Logically ANDs the source and the destination and stores the
		result in the destination.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Options:
		AN Rd,Rs	;the source and destination register must
				;belong to different register banks
		AN Rd,Im8
Examples:
		AN R10,R70
		AN R80,R20
		AN R25,I101
		AN I99,R44
		AN R16,&H55

--------------------

Mnemonic:	ANM (Logical AND Multibyte)
Syntax:		ANM dst,src
Execution:	dst <- dst AND src
Description:	Logically ANDs two register arrays and stores the result in
		the destination array. Both register arrays must belong to
		different register banks.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		ANM R0..R7,R64..R71
		ANM R83..R87,R51..R55
		ANM R33..R34,I81..I82
		ANM I109..I111,R45..R47

--------------------

Mnemonic:	BDN (Block Down)
Syntax:		BDN
Execution:
		+->  IX <- IX - 1
		|    IZ <- IZ - 1
		|    (IZ) <- (IX)
		+--  repeat if IX <> IY

Description:	Copies a block of memory where:
		IX = original block beginning (upper) address + 1
		IY = original block ending (lower) address
		IZ = destination beginning (upper) address + 1

Notes:		IX-register > IY-register
		Since the instruction opcode is repeatedly fetched and
		decoded, the interrupts can be serviced during the transfer.
		The instruction can be executed only from the microprocessor's
		internal ROM, otherwise it never terminates.

Flags:		none affected
Examples:
		LDW IX,&HCA00
		LDW IY,&HC800
		LDW IZ,&HD580
		CAL &H000A	;in the FX-8000G contains BDN followed by RTN
		; the memory block &HC800-&HC9FF will be copied to the address
		; &HD380-&HD57F (&H0200 bytes will be copied)
		; the contents of registers after executing the command:
		; IX=&HC800, IY=&HC800 (unchanged), IZ=&HD380

-------------------

Mnemonic:	BIT (Bit Test)
Syntax:		BIT dst, src
Execution:	NOT dst AND src
Description:	Logically ANDs the source and the negated destination, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Options:
		BIT Rd,Rs	;the source and destination register must
				;belong to different register banks
		BIT Rd,Im8
Examples:
		BIT R83,R17
		BIT R10,&H05		;Zero Flag if bits 0 and 2 of the
					;register R10 are set

--------------------

Mnemonic:	BIU (Bit Up)
Syntax:		BIU Reg
Execution:
	  _       _ _ _ _ _ _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <-- "0"
	Carry    MSB           LSB

Description:	Shifts the contents of a register one bit to the left. The
		least significant bit receives a 0, while the data from the
		most significant bit moves to the Carry flag register.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction AD.
Example:
		BIU R17

--------------------

Mnemonic:	BIUM (Bit Up Multibyte)
Syntax:		BIUM register array
Execution:
	  _       _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <--  "0"
	Carry    MSB                                       LSB

Description:	Shifts the contents of a register array one bit to the left.
		The least significant bit of the low-order byte receives a 0,
		while the data from the most significant bit of the high-order
		byte moves to the Carry flag register.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction ADM.
Examples:
		BIUM R98..R100
		BIUM I80..I87

--------------------

Mnemonic:	BNUSM (Byte Up then Swap Multibyte)
Syntax:		BNUSM register array
Execution:
	          _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _
	         MSB                                       LSB

Description:	Shifts the contents of a register array to the left in unit of
		bytes (the low-order byte remains unchanged), then swaps the
		digits in all registers of the array.
Flags:		none affected
Examples:
		LD R65,&H89
		LD R66,&HAB
		LD R67,&HCD
		LD R68,&HEF
		BNUSM R65..R68
		; the contents of registers after executing the command:
		; R65=&H98, R66=&H98, R67=&HBA, R68=&HDC

		BNUSM R19..R23
		BNUSM I76..I79

--------------------

Mnemonic:	BUP (Block Up)
Syntax:		BUP
Execution:
		+->  IX <- IX + 1
		|    IZ <- IZ + 1
		|    (IZ) <- (IX)
		+--  repeat if IX <> IY

Description:	Copies a block of memory where:
		IX = original block beginning (lower) address - 1
		IY = original block ending (upper) address
		IZ = destination beginning (lower) address - 1

Notes:		IX-register < IY-register
		Since the instruction opcode is repeatedly fetched and
		decoded, the interrupts can be serviced during the transfer.
		The instruction can be executed only from the microprocessor's
		internal ROM, otherwise it never terminates.

Flags:		none affected
Examples:
		LDW IX,&HC7FF
		LDW IY,&HC9FF
		LDW IZ,&HD37F
		CAL &H0008	;in the FX-8000G contains BUP followed by RTN
		; the memory block &HC800-&HC9FF will be copied to the address
		; &HD380-&HD57F (&H0200 bytes will be copied)
		; the contents of registers after executing the command:
		; IX=&HC9FF, IY=&HC9FF (unchanged), IZ=&HD57F

-------------------

Mnemonic:	BYD (Byte Down)
Syntax:		BYD Reg
Execution:
	                 _ _ _ _ _ _ _ _
	"00000000"  -->  _ _ _ _ _ _ _ _  -->  void
	                MSB           LSB

Description:	Writes 0 to a register.
Flags:		C=0, H=0, V=0, NZ=0, UZ=1, LZ=1
Example:
		BYD R17

--------------------

Mnemonic:	BYDM (Byte Down Multibyte)
Syntax:		BYDM register array
Execution:
	                 _ _ _  Rf _ _ _             _ _ _  Rl _ _ _
	"00000000"  -->  _ _ _ _ _ _ _ _  -> ... ->  _ _ _ _ _ _ _ _  --> void
	                MSB                                       LSB

Description:	Shifts the contents of a register array to the right in unit
		of bytes. The high-order byte receive O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		BYDM R67..R64		;R64 <- R65
					;R65 <- R66
					;R66 <- R67
					;R67 <- 0

		BYDM I119..I116

--------------------

Mnemonic:	BYU (Byte Up)
Syntax:		BYU Reg
Execution:
	           _ _ _ _ _ _ _ _
	void  <--  _ _ _ _ _ _ _ _  <--  "00000000"
	          MSB           LSB

Description:	Writes 0 to a register.
Flags:		C=0, H=0, V=0, NZ=0, UZ=1, LZ=1
Example:
		BYU R17

--------------------

Mnemonic:	BYUM (Byte Up Multibyte)
Syntax:		BYUM register array
Execution:
	          _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <--  "00000000"
	         MSB                                       LSB

Description:	Shifts the contents of a register array to the left in unit of
		bytes. The low-order byte receives O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		BYUM R11..R14		;R14 <- R13
					;R13 <- R12
					;R12 <- R11
					;R11 <- 0

		BYUM I82..I85

--------------------

Mnemonic:	CAL (Subroutine Call)
Syntax:		CAL Condition,Im16
Execution:	SP <- SP - 2
		(SP) <- PC
		PC <- Im16
Description:	Pushes the PC contents on the stack, then jumps to an address
		specified by 16-bit immediate data when the condition is met.
Flags:		none affected
Examples:
		CAL &H7D26	;unconditional call
		CAL C,&H7D26	;call on Carry (C=1)
		CAL NC,&H7D26	;call on Not Carry (C=0)
		CAL H,&H7D26	;call on Half Carry (H=1)
		CAL NH,&H7D26	;call on Not Half Carry (H=0)
		CAL V,&H7D26	;call on Overflow (V=1)
		CAL NV,&H7D26	;call on No Overflow (V=0)
		CAL NZ,&H7D26	;call on Not Zero (NZ=1)
		CAL Z,&H7D26	;call on Zero (NZ=0)
		CAL UZ,&H7D26	;call on Upper Zero (UZ=1)
		CAL NUZ,&H7D26	;call on Not Upper Zero (UZ=0)
		CAL LZ,&H7D26	;call on Lower Zero (LZ=1)
		CAL NLZ,&H7D26	;call on Not Lower Zero (LZ=0)
		CAL K,&H7D26	;call if key pressed (KI<>0)
		CAL NK,&H7D26	;call if key not pressed (KI=0)

--------------------

Mnemonic:	CANI (cancel interrupt)
Syntax:		CANI
Description:	Clears the hardware interrupt request latch which has the
		highest priority.
Flags:		none affected
Example:
		CANI

-------------------

Mnemonic:	CMP (Complement)
Syntax:		CMP Reg
Execution:	reg <- 0-reg
Description:	Provides a twos complement of the operand.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction SB, for example Carry is reset if result=0,
		set if result<>0.
Example:
		CMP R17

--------------------

Mnemonic:	CMPB (Complement BCD)
Syntax:		CMPB Reg
Execution:	reg <- 0-reg (decimal)
Description:	Negates a BCD number.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction SBB.
Example:
		CMPB R17

--------------------

Mnemonic:	CMPBM (Complement BCD Multibyte)
Syntax:		CMPBM dst
Execution:	register_array <- 0 - register_array (decimal)
Description:	Negates a BCD number in a register array.
		Note: This instruction doesn't allow indirect register array
		specification.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction SBBM.
Examples:
		CMPBM R17..R22
		CMPBM R84..R86

--------------------

Mnemonic:	CMPM (Complement Multibyte)
Syntax:		CMPM dst
Execution:	register_array <- 0 - register_array
Description:	Provides a twos complement of the register array.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction SBM.
Examples:
		CMPM R17..R22
		CMPM I81..I87

--------------------

Mnemonic:	DID (Digit Down)
Syntax:		DID Reg
Execution:
	             _ _ _ _ _ _ _ _
	"0000"  -->  _ _ _ _ _ _ _ _  -->  void
	            MSB           LSB

Description:	Shifts the contents of a register to the right by 4 bits. The
		high-order digit bits receive O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Example:
		DID R87

--------------------

Mnemonic:	DIDM (Digit Down Multibyte)
Syntax:		DIDM register array
Execution:
	             _ _ _  Rf _ _ _               _ _ _  Rl _ _ _
	"0000"  -->  _ _ _ _ _ _ _ _  --> ... -->  _ _ _ _ _ _ _ _  -> void
	            MSB                                         LSB

Description:	Shifts the contents of a register array to the right by
		4 bits. The high-order digit bits of the high-order byte
		receive O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		DIDM R20..R17
		DIDM I66..I64

--------------------

Mnemonic:	DIU (Digit Up)
Syntax:		DIU Reg
Execution:
	           _ _ _ _ _ _ _ _
	void  <--  _ _ _ _ _ _ _ _  <--  "0000"
	          MSB           LSB

Description:	Shifts the contents of a register to the left by 4 bits. The
		low-order digit bits receive O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Example:
		DIU R25

--------------------

Mnemonic:	DIUM (Digit Up Multibyte)
Syntax:		DIUM register array
Execution:
	          _ _ _  Rl _ _ _               _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <-- ... <--  _ _ _ _ _ _ _ _  <-- "0000"
	         MSB                                         LSB

Description:	Shifts the contents of a register array to the left by
		4 bits. The low-order digit bits of the low-order byte
		receive O's.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		DIUM R112..R119
		DIUM I77..I79

--------------------

Mnemonic:	GST (Get Status)
Syntax:		GST Reg,Sreg
Execution:	reg <- status_register
Description:	Reads the contents of a specified status register to a data
		register.
Flags:		none affected
Examples:
		GST R22,KO	;Keyboard Output Port
		GST R81,F	;Flags
		GST R45,AS	;Address Select Register
		GST R101,IE	;Interrupt Enable Register
		GST R95,KI	;Keyboard Input Port
		GST R10,IF	;Interrupt Flags

--------------------

Mnemonic:	IJMP (Indirect Jump)
Syntax:		IJMP 16-bit-register
Execution:	PC <- 16-bit-register
Description:	Indirect jump to the address pointed to by a 16-bit register
		when the condition is met.
Flags:		none affected
Examples:
		IJMP IX		;unconditional jump
		IJMP C,IY	;jump on Carry (C=1)
		IJMP NC,IZ	;jump on Not Carry (C=0)
		IJMP H,V3	;jump on Half Carry (H=1)
		IJMP NH,V2	;jump on Not Half Carry (H=0)
		IJMP V,V1	;jump on Overflow (V=1)
		IJMP NV,V0	;jump on No Overflow (V=0)
		IJMP NZ,SP	;jump on Not Zero (NZ=1)
		IJMP Z,R65,R1	;jump on Zero (NZ=0)
		IJMP UZ,R79,R15	;jump on Upper Zero (UZ=1)
		IJMP NUZ,IX	;jump on Not Upper Zero (UZ=0)
		IJMP LZ,IY	;jump on Lower Zero (LZ=1)
		IJMP NLZ,IZ	;jump on Not Lower Zero (LZ=0)
		IJMP K,V3	;jump if key pressed (KI<>0)
		IJMP NK,SP	;jump if key not pressed (KI=0)

--------------------

Mnemonic:	INV (Invert)
Syntax:		INV Reg
Execution:	reg <- not reg
Description:	Performs an ones complement of the operand (inverts the value
		of every bit in the register).
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Example:
		INV R33

--------------------

Mnemonic:	INVM (Invert)
Syntax:		INVM Reg
Execution:	register_array <- not register_array
Description:	Performs an ones complement of the operand (inverts the value
		of every bit in the register array).
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Examples:
		INVM R33..R35
		INVM I99..I100

--------------------

Mnemonic:	JMP (Absolute Jump)
Syntax:		JMP Condition,Im16
Execution:	PC <- Im16
Description:	Jumps to an address specified by 16-bit immediate data when
		the condition is met.
Flags:		none affected
Examples:
		JMP &H7D26	;unconditional jump
		JMP C,&H7D26	;jump on Carry (C=1)
		JMP NC,&H7D26	;jump on Not Carry (C=0)
		JMP H,&H7D26	;jump on Half Carry (H=1)
		JMP NH,&H7D26	;jump on Not Half Carry (H=0)
		JMP V,&H7D26	;jump on Overflow (V=1)
		JMP NV,&H7D26	;jump on No Overflow (V=0)
		JMP NZ,&H7D26	;jump on Not Zero (NZ=1)
		JMP Z,&H7D26	;jump on Zero (NZ=0)
		JMP UZ,&H7D26	;jump on Upper Zero (UZ=1)
		JMP NUZ,&H7D26	;jump on Not Upper Zero (UZ=0)
		JMP LZ,&H7D26	;jump on Lower Zero (LZ=1)
		JMP NLZ,&H7D26	;jump on Not Lower Zero (LZ=0)
		JMP K,&H7D26	;jump if key pressed (KI<>0)
		JMP NK,&H7D26	;jump if key not pressed (KI=0)

--------------------

Mnemonic:	LD (Load)
Syntax:		LD dst,src
Execution:	dst <- src
Description:	Transfers data to a register.
Flags:		none affected
Options:
		LD Rd,Rs		;the source and destination register
					;must belong to different banks

		LD Rd,Im8

		LD Rd,(IX)-
		LD Rd,(IY)-
		LD Rd,(IZ)-
		LD Rd,(SP)-
		
		LD Rd,(IX)+
		LD Rd,(IY)+
		LD Rd,(IZ)+
		LD Rd,(SP)+		;can be noted as POP Rd

		LD Rd,(IX+/-Im8)	;immediate offset in range 0..255
		LD Rd,(IY+/-Im8)
		LD Rd,(IZ+/-Im8)
		LD Rd,(SP+/-Im8)

		LD Rd,(IX+/-Ri)		;the destination register belongs
		LD Rd,(IY+/-Ri)		;to the bank 1
		LD Rd,(IZ+/-Ri)		;the index register belongs to the
		LD Rd,(SP+/-Ri)		;bank 0
Examples:
		LD R10,R70
		LD R80,R20
		LD R25,I120
		LD I121,R44
		LD R16,&H55
		LD R110,(IX)+		;R110 <- (IX); IX <- IX + 1
		LD R47,(IY)-		;R47 <- (IY); IY <- IY - 1
		LD R22,(IX+&H43)
		LD R99,(IZ-255)
		LD R75,(IX+R27)
		LD R103,(IZ-R12)
		LD I110,(IY+R44)

--------------------

Mnemonic:	LDLE (Load from the LCD bus, Even number of nibbles)
Syntax:		LDLE register,immediate_byte
Purpose:	Reads the LCD data port to the register (two 4-bit nibbles,
		the lower nibble first). The LCD control port is set according
		to the immediate operand.
Flags:		none affected
Example:
		LDLE R8,&H01	;control port: OP=0, CE1=1

--------------------

Mnemonic:	LDLEM (Load from the LCD bus, Even number of nibbles,
		Multibyte)
Syntax:		LDLEM register_array,6-bit_immediate_data
Purpose:	Reads the LCD data port to the register array. The LCD control
		port is set according to the immediate operand.
Flags:		none affected
Examples:
		LDLEM R64..R71,&H01	;16 data nibbles will be read
					;control port: OP=0, CE1=1

--------------------

Mnemonic:	LDLO (Load from the LCD bus, Odd number of nibbles)
Syntax:		LDLO register,immediate_byte
Purpose:	Reads a single 4-bit nibble from the LCD data port to the
		register. The LCD control port is set according to the
		immediate operand.
Flags:		none affected
Example:
		LDLO R95,&H01	;control port: OP=0, CE1=1

--------------------

Mnemonic:	LDLOM (Load from the LCD bus, Odd number of nibbles,
		Multibyte)
Syntax:		LDLOM register_array,6-bit_immediate_data
Purpose:	Reads the LCD data port to the register array. The LCD control
		port is set according to the immediate operand.
Flags:		none affected
Examples:
		LDLOM R64..R71,&H01	;15 data nibbles will be read
					;control port: OP=0, CE1=1

--------------------

Mnemonic:	LDM (Load Multibyte)
Syntax:		LDM dst,src
Execution:	register array <- source
Description:	Transfers up to 8 bytes to an array of data registers.
		Note: The instruction encoding scheme allows to specify the
		destination array indirectly for the indexed source mode as
		well, but the result doesn't work as expected.
Flags:		none affected
Options:
		LDM Rf..Rl,Im6		;load 6-bit immediate data to all
					;registers of directly specified array

		LDM Rdf..Rdl,Rsf..Rsl	;the source and destination arrays
					;must belong to different banks

		LDM Rf..Rl,(IX)-
		LDM Rf..Rl,(IY)-
		LDM Rf..Rl,(IZ)-
		LDM Rf..Rl,(SP)-

		LDM Rf..Rl,(IX)+
		LDM Rf..Rl,(IY)+
		LDM Rf..Rl,(IZ)+
		LDM Rf..Rl,(SP)+

		LDM Rf..Rl,(IX+/-Im6)	;the destination register array
		LDM Rf..Rl,(IY+/-Im6)	;belongs to the bank 0,
		LDM Rf..Rl,(IZ+/-Im6)	;immediate offset in range 0..63
		LDM Rf..Rl,(SP+/-Im6)

		LDM Rf..Rl,(IX+/-Ri)	;the destination register array
		LDM Rf..Rl,(IY+/-Ri)	;belongs to the bank 1,
		LDM Rf..Rl,(IZ+/-Ri)	;the index register belongs to the
		LDM Rf..Rl,(SP+/-Ri)	;bank 0, must be aligned with Rf

Examples:
		;immediate data to a single register array
		LDM R16..R18,&H0F	;R16 <- &H0F
					;R17 <- &H0F
					;R18 <- &H0F

		;register array to register array
		LDM R16..R18,R48..R50	;R16 <- R48
					;R17 <- R49
					;R18 <- R50

		;register array to indirectly specified register array
		PST AS,&H54		;AS points to R106
		LDM I64..I66,R16..R18	;R106 <- R16
					;R107 <- R17
					;R108 <- R18

		;indirectly specified register array to register array
		PST AS,&H05
		; address of the starting source register = 96+2
		LDM R45..R47,I101..I103	;R45 <- R98
					;R46 <- R99
					;R47 <- R100

		LDM R16..R18,(IX)+	;R16 <- (IX); IX <- IX + 1
					;R17 <- (IX); IX <- IX + 1
					;R18 <- (IX); IX <- IX + 1

		LDM R84..R81,(IY)-	;R84 <- (IY); IY <- IY - 1
					;R83 <- (IY); IY <- IY - 1
					;R82 <- (IY); IY <- IY - 1
					;R81 <- (IY); IY <- IY - 1

		;indexed address modes, positive offset
		LDM R21..R23,(IX+4)	;R21 <- (IX+4)
					;R22 <- (IX+5)
					;R23 <- (IX+6)

		LD R10,135
		LDM R82..R84,(IY+R10)	;R82 <- (IY+135)
					;R83 <- (IY+136)
					;R84 <- (IY+137)

		;indexed address modes, negative offset
		LDM R38..R36,(IZ-7)	;R38 <- (IZ-7)
					;R37 <- (IZ-8)
					;R36 <- (IZ-9)

		LD R44,15
		LDM R68..R66,(IX-R44)	;R68 <- (IX-15)
					;R67 <- (IX-16)
					;R66 <- (IX-17)

--------------------

Mnemonic:	LDW (Load Word)
Syntax:		LDW dst,src
Execution:	dst <- src
Description:	Transfers immediate data to a 16-bit register.
Flags:		none affected
Options:
		LDW IX,Im16
		LDW IY,Im16
		LDW IZ,Im16
		LDW V3,Im16
		LDW V2,Im16
		LDW V1,Im16
		LDW V0,Im16
		LDW SP,Im16
Examples:
		LDW IX,&H8000
		LDW SP,&HDFFF

--------------------

Mnemonic:	MTB (Multiply by Two BCD)
Syntax:		MTB Reg
Execution:	Reg <- Reg * 2 , produces decimal result
Description:	Multiplies the contents of the register by two. The register
		is assumed to contain two digits in binary-coded decimal (BCD)
		form.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction ADB.
Example:
		MTB R89

--------------------

Mnemonic:	MTBM (Multiply by Two BCD Multibyte)
Syntax:		MTBM register array
Execution:	register_array <- register_array * 2 , produces decimal result
Description:	Multiplies the contents of the register array by two. Each
		byte is assumed to contain two digits in binary-coded decimal
		(BCD) form.
		Note: This instruction doesn't allow indirect register array
		specification.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction ADBM.
Example:
		MTBM R19..R23

--------------------

Mnemonic:	NA (Logical NAND)
Syntax:		NA dst,src
Execution:	dst <- NOT (dst AND src)
Description:	Logically NANDs the source and the destination and stores the
		result in the destination.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Options:
		NA Rd,Rs	;the source and destination register must
				;belong to different register banks
		NA Rd,Im8
Examples:
		NA R10,R70
		NA R80,R20
		NA R25,I77
		NA I91,R44
		NA R16,&H55

--------------------

Mnemonic:	NAM (Logical NAND Multibyte)
Syntax:		NAM dst,src
Execution:	dst <- NOT (dst AND src)
Description:	Logically NANDs the source and the destination array and
		stores the result in the destination array. Both arrays must
		belong to different register banks.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Examples:
		NAM R10..R12,R74..R76
		NAM I83..I84,R27..R28
		NAM R48..R55,I80..I87

-------------------

Mnemonic:	NOP (no operation)
Syntax:		NOP
Description:	Increments the program counter.
Flags:		none affected
Example:
		NOP

-------------------

Mnemonic:	OFF (Power Off)
Syntax:		OFF
Description:	Puts the microprocessor into sleep mode. Following registers
		are changed:
		- KO <- &H41 (active KO output)
		- IF <- &H00 (EN1 and EN2 inactive)
		The processor can be waken up (i.e. restarted from the address
		&H0000) by following events:
		- voltage level change on the INT2 input from high to low
		- pressing the [AC] key, i.e. voltage level change on the KI0
		  input from high to low
		- turning the power switch off then on, i.e. voltage level
		  change on the SW input from high to low
Example:
		OFF

-------------------

Mnemonic:	OR (Logical OR)
Syntax:		OR dst,src
Execution:	dst <- dst OR src
Description:	Logically ORs the source and the destination and stores the
		result in the destination.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Options:
		OR Rd,Rs	;the source and destination register must
				;belong to different register banks
		OR Rd,Im8
Examples:
		OR R10,R70
		OR R80,R20
		OR R25,I64
		OR I71,R44
		OR R16,&H55

--------------------

Mnemonic:	ORM (Logical OR Multibyte)
Syntax:		ORM dst,src
Execution:	dst <- dst OR src
Description:	Logically ORs two register arrays and stores the result in
		the destination array. Both arrays must belong to different
		register banks.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Examples:
		ORM R41..R44,R97..R100
		ORM R0..R7,I72..I79
		ORM I98..I98,R58..R58

--------------------

Mnemonic:	PST (Put Status)
Syntax:		PST Sreg,src
Execution:	status_register <- src
Description:	Writes data to a specified status register.
Flags:		none affected except when writting to the F register
Options:
		PST Sreg,Rs
		PST Sreg,Im8
Examples:
		PST KO,R31	;Keyboard Output Port
		PST KO,&H48	;select the key output KO4

		PST F,R81	;Flags (register operand only)
		PST IF,&H10	;ENx port control (immediate operand only)

		PST AS,R45	;Addres Select Register
		PST AS,&H02	;point to R65

		PST IE,R101	;Interrupt Enable Register
		PST IE,&H20	;enable INT1 interrupts

--------------------

Mnemonic:	ROD (Rotate Down)
Syntax:		ROD Reg
Execution:

	+ - - - - - - - - - - - - - - - +
	|   _       _ _ _ _ _ _ _ _     |
	+ - _  -->  _ _ _ _ _ _ _ _  -> +
	  Carry    MSB           LSB

Description:	Circulary shifts the register contents one bit to the right.
Flags:		C changes, H=0, V=0, NZ, UZ and LZ change
Example:
		ROD R17

--------------------

Mnemonic:	RODM (Rotate Down Multibyte)
Syntax:		RODM Reg
Execution:

	+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
	|   _       _ _ _  Rf _ _ _             _ _ _  Rl _ _ _     |
	+ - _  -->  _ _ _ _ _ _ _ _  -> ... ->  _ _ _ _ _ _ _ _  -> +
	  Carry    MSB                                       LSB

Description:	Circulary shifts a register array one bit to the right.
		Note: the instruction doesn't work as expected. Actually
		the shifted-out bit is erroneously subtracted from the next
		register before shifting-in.
Flags:		C changes, H=0, V=0, NZ, UZ and LZ change
Examples:
		TOR  R64,&H00	;set Carry
		LD   R19,&H00
		LD   R20,&H70
		RODM R20..R19
		; R20=&H83
		; R19=&HFF instead of &H80

		RODM I99..I97

--------------------

Mnemonic:	ROU (Rotate Up)
Syntax:		ROU Reg
Execution:

	+ - - - - - - - - - - - - - - - +
	|   _       _ _ _ _ _ _ _ _     |
	+ - _  <--  _ _ _ _ _ _ _ _  <- +
	  Carry    MSB           LSB

Description:	Circulary shifts the register contents one bit to the left.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent reg+reg+carry operation.
Example:
		ROU R93

--------------------

Mnemonic:	ROUM (Rotate Up Multibyte)
Syntax:		ROUM Reg
Execution:

	+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
	|   _       _ _ _  Rl _ _ _             _ _ _  Rf _ _ _     |
	+ - _  <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <- +
	  Carry    MSB                                       LSB

Description:	Circulary shifts the contents of a register array one bit to
		the left.
Flags:		C, H, V, NZ, UZ and LZ change
		Flags are set as by equivalent array+array+carry operation.
Examples:
		ROUM R34..R37
		ROUM I65..I68

--------------------

Mnemonic:	RTN (Return From Subroutine)
Syntax:		RTN
Execution:	PC <- (SP)
		SP <- SP + 2
Description:	Returns from a subroutine.
Flags:		none affected
Example:
		RTN

--------------------

Mnemonic:	SB (Subtract)
Syntax:		SB dst,src
Execution:	dst <- dst - src
Description:	Subtracts the source from the destination and stores the
		result in the destination.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		SB Rd,Rs	;the source and destination register must
				;belong to different register banks
		SB Rd,Im8
Examples:
		SB R10,R70
		SB R80,R20
		SB R25,I112
		SB I67,R44
		SB R16,&H55

--------------------

Mnemonic:	SBB (Subtract BCD)
Syntax:		SBB dst,src
Execution:	dst <- dst - src, produces a decimal result
Description:	Subtracts the source from the destination, and stores the
		result in the destination. Each byte is assumed to contain
		two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		SBB Rd,Rs	;the source and destination register must
				;belong to different register banks
		SBB Rd,Im8
Examples:
		SBB R10,R70
		SBB R80,R20
		SBB R25,I88
		SBB I92,R44
		SBB R16,&H55

--------------------

Mnemonic:	SBBM (Subtract BCD Multibyte)
Syntax:		SBBM dst,src
Execution:	dst <- dst - src, produces a decimal result
Description:	Subtracts the source from the destination array, and stores
		the result in the destination array. Each byte is assumed to
		contain two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		SBBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		SBBM R8..R15,R72..R79
		SBBM R75..R78,&H07
		SBBM R24..R31,I96..I111
		SBBM I99..I101,R43..R45

--------------------

Mnemonic:	SBM (Subtract Multibyte)
Syntax:		SBM dst,src
Execution:	dst <- dst - src
Description:	Subtracts the source from the destination array and stores
		the result in the destination array.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		SBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		SBM R10..R11,R74..R75
		SBM R88..R95,&H2B
		SBM R24..R31,I88..I95
		SBM I99..I101,R43..R45

--------------------

Mnemonic:	SBW (Subtract Word)
Syntax:		SBW dst,Im8
Execution:	dst <- dst - Im8
Description:	Subtracts the 8-bit immediate data from the 16-bit index
		register and stores the result in the index register.
Flags:		none affected
Options:
		SBW IX,Im8
		SBW IY,Im8
		SBW IZ,Im8
		SBW SP,Im8
Examples:
		SBW IX,&H5A		;IX <- IX - &H5A
		SBW SP,&HF0		;SP <- SP - &HF0

--------------------

Mnemonic:	SDN (Search Down)
Syntax:		SDN Reg
Execution:
		+->  IX <- IX - 1
		|
		+--  repeat if IX <> IY and Reg <> (IX)

Description:	Searches the memory for specified data.
		IX-register = beginning (upper) address + 1
		IY-register = ending (lower) address
		Reg = searched data specified in the register belonging to
		the bank 0

Notes:		Since the instruction opcode is repeatedly fetched and
		decoded, the interrupts can be serviced during the search.
		The instruction can be executed only from the microprocessor's
		internal ROM, otherwise it never terminates.

Flags:		none affected
Example:
		LD R0,&H45	;searched data
		LDW IX,&HD801	;beginning address + 1
		LDW IY,&HD600	;ending address
		CAL &H000E	;in the FX-8000G contains SDN R0 + RTN
		; the contents of registers after executing the command:
		; IX=&HD600 if data not found
		; IX=&HD71F if data found at location &HD71F

--------------------

Mnemonic:	ST (Store)
Syntax:		ST dst,src
Execution:	dst <- src
Description:	Transfers data to a memory location.
Flags:		none affected
Options:
		ST -(IX),Rs
		ST -(IY),Rs
		ST -(IZ),Rs
		ST -(SP),Rs		;can be noted as PUSH Rs

		ST +(IX),Rs
		ST +(IY),Rs
		ST +(IZ),Rs
		ST +(SP),Rs

		ST (IX+/-Im8),Rs	;immediate offset in range 0..255
		ST (IY+/-Im8),Rs
		ST (IZ+/-Im8),Rs
		ST (SP+/-Im8),Rs

		ST (IX+/-Ri),Rs		;the index register belongs to the
		ST (IY+/-Ri),Rs		;register bank 0
		ST (IZ+/-Ri),Rs		;the source register belongs to the
		ST (SP+/-Ri),Rs		;register bank 1

		ST (IX),Im8
		ST (IY),Im8
		ST (IZ),Im8
		ST (SP),Im8

		ST +(IX),Im8
		ST +(IY),Im8
		ST +(IZ),Im8
		ST +(SP),Im8

		ST -(IX),Im8
		ST -(IY),Im8
		ST -(IZ),Im8
		ST -(SP),Im8
Examples:
		ST +(IX),R110		;IX <- IX + 1; (IX) <- R110
		ST -(IY),R47		;IY <- IY - 1; (IY) <- R47
		ST (IY+100),R25
		ST (SP-&H12),R68
		ST (IY+R10),R95
		ST (SP-R30),R88
		ST (IZ+R50),I100
		ST (IX),&H80
		ST +(IY),1		;IY <- IY + 1; (IY) <- &H01
		ST -(SP),&HC0		;SP <- SP - 1; (SP) <- &HC0

--------------------

Mnemonic:	STLE (Store to the LCD bus, Even number of nibbles)
Syntax:		STLE register,immediate_byte
Purpose:	Transfers the contents of a register to the LCD data area (two
		4-bit nibbles, the lower nibble is transmitted first). The LCD
		control port is set according to the immediate operand.
Flags:		none affected
Example:
		LD R8,&H14
		STLE R8,&H21	;transferred data: &H4, &H1
				;control port: OP=1, CE1=1

--------------------

Mnemonic:	STLEM (Store to the LCD bus, Even number of nibbles,
		Multibyte)
Syntax:		STLEM register_array,6-bit_immediate_data
Purpose:	Transfers the contents of a register array to the LCD data
		area. The LCD control port is set according to the immediate
		operand.
Flags:		none affected
Examples:
		LD R96,&H56
		LD R97,&H78
		STLEM R96..R97,&H01	;transferred data: &H6, &H5, &H8, &H7
					;control port: OP=0, CE1=1

--------------------

Mnemonic:	STLO (Store to the LCD bus, Odd number of nibbles)
Syntax:		STLO register,immediate_byte
Purpose:	Transfers the lower 4-bit nibble of a register to the LCD data
		area. The LCD control port is set according to the immediate
		operand.
Flags:		none affected
Example:
		LD R95,&H0A
		STLO R95,&H01	;transferred data: &HA
				;control port: OP=0, CE1=1

--------------------

Mnemonic:	STLOM (Store to the LCD bus, Odd number of nibbles, Multibyte)
Syntax:		STLOM register_array,6-bit_immediate_data
Purpose:	Transfers the contents of a register array to the LCD data
		area. The upper 4-bit nibble of the last register isn't
		transferred. The LCD control port is set according to the
		immediate operand.
Flags:		none affected
Examples:
		LD R96,&H56
		LD R97,&H07
		STLOM R96..R97,&H21	;transferred data: &H6, &H5, &H7
					;control port: OP=1, CE1=1

--------------------

Mnemonic:	STM (Store Multibyte)
Syntax:		STM dst,src
Execution:	memory block <- register array
Description:	Transfers an array of up to 8 data registers to memory.
		Note: The instruction encoding scheme allows to specify the
		source array indirectly as well, but the result doesn't work
		as expected.
Flags:		none affected
Options:
		STM -(IX),Rf..Rl
		STM -(IY),Rf..Rl
		STM -(IZ),Rf..Rl
		STM -(SP),Rf..Rl

		STM +(IX),Rf..Rl
		STM +(IY),Rf..Rl
		STM +(IZ),Rf..Rl
		STM +(SP),Rf..Rl

		STM (IX+/-Im6),Rf..Rl	;immediate offset in range 0..63
		STM (IY+/-Im6),Rf..Rl	;the source register array belongs
		STM (IZ+/-Im6),Rf..Rl	;to the bank 0
		STM (SP+/-Im6),Rf..Rl

		STM (IX+/-Ri),Rf..Rl	;the index register belongs to the
		STM (IY+/-Ri),Rf..Rl	;bank 0, must be aligned with Rf
		STM (IZ+/-Ri),Rf..Rl	;the source register array belongs
		STM (SP+/-Ri),Rf..Rl	;to the bank 1

Examples:
		STM +(IX),R16..R18	;IX <- IX + 1; (IX) <- R16
					;IX <- IX + 1; (IX) <- R17
					;IX <- IX + 1; (IX) <- R18

		STM -(IY),R84..R81	;IY <- IY - 1; (IY) <- R84
					;IY <- IY - 1; (IY) <- R83
					;IY <- IY - 1; (IY) <- R82
					;IY <- IY - 1; (IY) <- R81

		;indexed address modes, positive offset
		STM (IX+4),R21..R23	;(IX+4) <- R21
					;(IX+5) <- R22
					;(IX+6) <- R23

		LD R10,35
		STM (IY+R10),R82..R84	;(IY+35) <- R82
					;(IY+36) <- R83
					;(IY+37) <- R84

		;indexed address modes, negative offset
		STM (IZ-7),R38..R36	;(IZ-7) <- R38
					;(IZ-8) <- R37
					;(IZ-9) <- R36

		LD R44,15
		STM (IX-R44),R68..R66	;(IX-15) <- R68
					;(IX-16) <- R67
					;(IX-17) <- R66

--------------------

Mnemonic:	SUP (Search Up)
Syntax:		SUP Reg
Execution:
		+->  IX <- IX + 1
		|
		+--  repeat if IX <> IY and Reg <> (IX)

Description:	Searches the memory for specified data.
		IX-register = beginning (lower) address - 1
		IY-register = ending (upper) address
		Reg = searched data specified in the register belonging to
		the bank 1

Notes:		Since the instruction opcode is repeatedly fetched and
		decoded, the interrupts can be serviced during the search.
		The instruction can be executed only from the microprocessor's
		internal ROM, otherwise it never terminates.

Flags:		none affected
Example:
		LD R64,&H45	;searched data
		LDW IX,&HD77F	;beginning address - 1
		LDW IY,&HDA00	;ending address
		CAL &H000C	;in the FX-8000G contains SUP R64 + RTN
		; the contents of registers after executing the command:
		; IX=&HDA00 if data not found
		; IX=&HD825 if data found at location &HD825

--------------------

Mnemonic:	SWP (Swap Digits)
Syntax:		SWP reg
		SWP reg1, reg2
Execution:	swap digits
Description:	Swaps digits in specified register(s).
Flags:		none affected
Options:
		SWP Rd		;swap digits in a single register
		SWP Rd,Rs	;swap digits in two registers which must
				;belong to different banks
Examples:
		SWP R15
		SWP R99
		SWP R10,R70
		SWP R80,R20
		SWP R25,I105
		SWP I70,R44

--------------------

Mnemonic:	SWPM (Swap Digits Multibyte)
Syntax:		SWPM register_array1, register_array2
Execution:	swap digits
Description:	Swaps digits in all registers of specified register arrays.
		Both arrays must belong to different register banks.
Flags:		none affected
Examples:
		SWPM R10..R15,R72..R77
		SWPM R82..R85,R26..R29
		SWPM R10..R15,I90..I95
		SWPM I98..I101,R26..R29

--------------------

Mnemonic:	TAD (Test Add)
Syntax:		TAD dst,src
Execution:	dst + src
Description:	Adds the source to the destination, but the result is not
		written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TAD Rd,Rs	;the source and destination register must
				;belong to different register banks
		TAD Rd,Im8
Examples:
		TAD R10,R70
		TAD R80,R20
		TAD R25,I81
		TAD I73,R44
		TAD R16,&H55

--------------------

Mnemonic:	TADB (Test Add BCD)
Syntax:		TADB dst,src
Execution:	dst + src, decimal numbers
Description:	Adds the source to the destination, but the result is not
		written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TADB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TADB Rd,Im8
Examples:
		TADB R10,R70
		TADB R80,R20
		TADB R25,I89
		TADB I73,R44
		TADB R16,&H55

--------------------

Mnemonic:	TADBM (Add BCD Multibyte)
Syntax:		TADBM dst,src
Execution:	dst + src, decimal numbers
Description:	Adds the source to the destination array, but the result is
		not written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TADBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TADBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		TADBM R0..R3,R64..R67
		TADBM R64..R66,&H14
		TADBM R0..R3,I96..I99
		TADBM I104..I105,R56..R57

--------------------

Mnemonic:	TADM (Test Add Multibyte)
Syntax:		TADM dst,src
Execution:	dst + src
Description:	Adds the sorce to the destination array, but the result is not
		written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TADM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TADM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		TADM R100..R103,R44..R47
		TADM R11..R14,&H2A
		TADM I108..I111,R44..R47
		TADM R24..R31,I88..I95

--------------------

Mnemonic:	TAN (Test Logical AND)
Syntax:		TAN dst,src
Execution:	dst AND src
Description:	Logically ANDs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Options:
		TAN Rd,Rs	;the source and destination register must
				;belong to different register banks
		TAN Rd,Im8
Examples:
		TAN R10,R70
		TAN R80,R20
		TAN R25,I70
		TAN I80,R44
		TAN R16,&H55

--------------------

Mnemonic:	TANM (Test Logical AND Multibyte)
Syntax:		TANM dst,src
Execution:	dst AND src
Description:	Logically ANDs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both register arrays must belong to different register banks.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		TANM R0..R7,R64..R71
		TANM R0..R7,I64..I71
		TANM I65..I70,R49..R54

--------------------

Mnemonic:	TNA (Test Logical NAND)
Syntax:		TNA dst,src
Execution:	NOT (dst AND src)
Description:	Logically NANDs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Options:
		TNA Rd,Rs	;the source and destination register must
				;belong to different register banks
		TNA Rd,Im8
Examples:
		TNA R10,R70
		TNA R80,R20
		TNA R25,I85
		TNA I99,R44
		TNA R16,&H55

--------------------

Mnemonic:	TNAM (Test Logical NAND Multibyte)
Syntax:		TNAM dst,src
Execution:	NOT (dst AND src)
Description:	Logically NANDs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Examples:
		TNAM R10..R12,R74..R76
		TNAM R80..R87,R32..R39
		TNAM R10..R13,I98..I101
		TNAM I80..I87,R32..R39

--------------------

Mnemonic:	TOR (Test Logical OR)
Syntax:		TOR dst,src
Execution:	dst OR src
Description:	Logically ORs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Options:
		TOR Rd,Rs	;the source and destination register must
				;belong to different register banks
		TOR Rd,Im8
Examples:
		TOR R10,R70
		TOR R80,R20
		TOR R25,I99
		TOR I86,R44
		TOR R16,&H55

--------------------

Mnemonic:	TORM (Test Logical OR Multibyte)
Syntax:		TORM dst,src
Execution:	dst OR src
Description:	Logically ORs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=1, H=1, V=1, NZ, UZ and LZ change
Examples:
		TORM R41..R44,R97..R100
		TORM R84..R87,R12..R15
		TORM R41..R45,I73..I77
		TORM I84..I87,R12..R15

--------------------

Mnemonic:	TRP (Trap)
Syntax:		TRP
Description:	Pushes the PC contents on the stack, then jumps to an address
		contained in the V3 register.
Flags:		none affected
Example:
		TRP

--------------------

Mnemonic:	TSB (Test Subtract)
Syntax:		TSB dst,src
Execution:	dst - src
Description:	Subtracts the source from the destination, but the result is
		not written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TSB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSB Rd,Im8
Examples:
		TSB R10,R70
		TSB R80,R20
		TSB R25,I64
		TSB I123,R44
		TSB R16,&H55

--------------------

Mnemonic:	TSBB (Test Subtract BCD)
Syntax:		TSBB dst,src
Execution:	dst - src, decimal numbers
Description:	Subtracts the source from the destination, but the result is
		not written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TSBB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSBB Rd,Im8
Examples:
		TSBB R10,R70
		TSBB R80,R20
		TSBB R25,I76
		TSBB I75,R44
		TSBB R16,&H55

--------------------

Mnemonic:	TSBBM (Test Subtract BCD Multibyte)
Syntax:		TSBBM dst,src
Execution:	dst - src, decimal numbers
Description:	Subtracts the source from the destination array, but the
		result is not written anywhere. Only the status of the flags
		is changed. Each byte is assumed to contain two digits in
		binary-coded decimal (BCD) form.
Flags:		C, H, V, NZ, UZ and LZ change
Options:
		TSBBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TSBBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		TSBBM R8..R15,R72..R79
		TSBBM R72..R79,&H36
		TSBBM R8..R15,I72..I79
		TSBBM I70..I71,R38..R39

--------------------

Mnemonic:	TSBM (Test Subtract Multibyte)
Syntax:		TSBM dst,src
Execution:	dst - src
Description:	Subtracts the source from the destination array, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C, H, V, NZ, UZ and LZ change
		TSBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TSBM Rdf..Rdl,Im6	;immediate 6-bit operand
Examples:
		TSBM R10..R11,R74..R75
		TSBM R64..R66,&H0F
		TSBM R10..R11,I74..I75
		TSBM I89..I95,R17..R23

--------------------

Mnemonic:	TXR (Test Logical XOR)
Syntax:		TXR dst,src
Execution:	dst XOR src
Description:	Logically XORs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Options:
		TXR Rd,Rs	;the source and destination register must
				;belong to different register banks
		TXR Rd,Im8
Examples:
		TXR R10,R70
		TXR R80,R20
		TXR R25,I99
		TXR I88,R44
		TXR R16,&H55

--------------------

Mnemonic:	TXRM (Test Logical XOR Multibyte)
Syntax:		TXRM dst,src
Execution:	dst XOR src
Description:	Logically XORs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		TXRM R84..R87,R20..R23
		TXRM I84..I87,R20..R23
		TXRM R33..R35,I65..I67

--------------------

Mnemonic:	XC (Exchange bytes)
Syntax:		XC reg1,reg2
Execution:	reg1 <-> reg2
Description:	Exchanges the contents of two registers.
Flags:		none affected
Options:
		XC Rd,Rs	;both registers must belong to different banks
Examples:
		XC R10,R70
		XC R80,R20
		XC R25,I99
		XC I88,R44

--------------------

Mnemonic:	XCHS (Exchange Higher Digit then Swap Digits)
Syntax:		XCHS dst,src
Execution:	lower digit of dst <-> upper digit of src,
		swap digits both in dst and src
Description:	Exchanges the upper digit of the source register with the
		lower digit of the destination register, then swaps digits in
		both registers. The registers must belong to different banks.
Flags:		none affected
Examples:
		LD R80,&HAB
		LD R16,&HCD
		XCHS R80,R16
		;R80 = &HCA
		;R16 = &HDB
		;it's a rotation of four digits (nibbles) clockwise

		Note: instructions XCHS R80,R16 and XCLS R16,R80 are
		      equivalent

		XCHS R10,R70
		XCHS R25,I99
		XCHS I88,R44

--------------------

Mnemonic:	XCHSM (Exchange Higher Digits then Swap Digits, Multibyte)
Syntax:		XCHSM dst,src
Execution:	lower digits of dst <-> upper digits of src,
		swap digits both in dst and src
Description:	Exchanges the upper digits of the source register array with
		the lower digits of the destination register array, then swaps
		digits in all registers of both arrays. The arrays must belong
		to different banks.
Flags:		none affected
Examples:
		LD R84,&H67
		LD R85,&H89
		LD R20,&HAB
		LD R21,&HCD
		XCHSM R84..R85,R20..R21	;R84=&HA6, R85=&HC8
					;R20=&HB7, R21=&HD9

		Note: instructions XCHSM R84..R85,R20..R21 and
		      XCLSM R20..R21,R84..R85 are equivalent

		XCHSM I84..I85,R20..R21
		XCHSM R48..R55,I80..I87

--------------------

Mnemonic:	XCLS (Exchange Lower Digit then Swap Digits)
Syntax:		XCLS dst,src
Execution:	upper digit of dst <-> lower digit of src,
		swap digits both in dst and src
Description:	Exchanges the lower digit of the source register with the
		upper digit of the destination register, then swaps digits in
		both registers. The registers must belong to different banks.
Flags:		none affected
Examples:
		LD R80,&HAB
		LD R20,&HCD
		XCLS R80,R20
		;R80 = &HBD
		;R20 = &HAC
		;it's a rotation of four digits (nibbles) counterclockwise

		Note: instructions XCLS R80,R20 and XCHS R20,R80 are
		      equivalent

		XCLS R10,R70
		XCLS R25,I99
		XCLS I88,R44

--------------------

Mnemonic:	XCLSM (Exchange Lower Digits then Swap Digits, Multibyte)
Syntax:		XCLSM dst,src
Execution:	upper digits of dst <-> lower digits of src,
		swap digits both in dst and src
Description:	Exchanges the lower digits of the source register array with
		the upper digits of the destination register array, then swaps
		digits in all registers of both arrays. The arrays must belong
		to different banks.
Flags:		none affected
Examples:
		LD R80,&H34
		LD R81,&H56
		LD R24,&HAB
		LD R25,&HCD
		XCLSM R80..R81,R24..R25	;R80=&H4B, R81=&H6D
					;R24=&H3A, R25=&H5C

		Note: instructions XCLSM R80..R81,R24..R25 and
		      XCHSM R24..R25,R80..R81 are equivalent

		XCLSM I96..I97,R24..R25
		XCLSM R3..R6,I83..I86

--------------------

Mnemonic:	XCM (Exchange Multibyte)
Syntax:		XCM dst,src
Execution:	register array 1 <-> register array 2
Description:	Exchanges the contents of two register arrays. Both arrays
		must belong to different register banks.
Flags:		none affected
Examples:
		XCM R10..R13,R74..R77	;R10 <-> R74
					;R11 <-> R75
					;R12 <-> R76
					;R13 <-> R77

		XCM R10..R13,I82..I85
		XCM I64..I66,R56..R58

--------------------

Mnemonic:	XR (Logical XOR)
Syntax:		XR dst,src
Execution:	dst <- dst XOR src
Description:	Logically XORs the source and the destination and stores the
		result in the destination.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Options:
		XR Rd,Rs	;the source and destination register must
				;belong to different register banks
		XR Rd,Im8
Examples:
		XR R10,R70
		XR R80,R20
		XR R25,I99
		XR I88,R44
		XR R16,&H55

--------------------

Mnemonic:	XRM (Logical XOR Multibyte)
Syntax:		XRM dst,src
Execution:	dst <- dst XOR src
Description:	Logically XORs the source and the destination array and stores
		the result in the destination array. Both arrays must belong
		to different register banks.
Flags:		C=0, H=0, V=0, NZ, UZ and LZ change
Examples:
		XRM R84..R87,R20..R23
		XRM I100..I103,R20..R23
		XRM R8..R15,I72..I79

--------------------

