Microprocessor Casio NM-320 / uPD1007 instruction encoding
All numbers are hexadecimal unless stated otherwise.
Most mnemonic names were adopted from the Casio's HD61700 official instruction
set.



Opcode vs Instruction Cross Reference
=====================================


opcode	#bytes	#cycles	addr. mode	mnemonic
------	------	-------	----------	--------

Instructions selected by cleared bit 7 of the second byte
---------------------------------------------------------

; the destination register specified by the third operand byte (RB1)
; the source register specified by the second operand byte (RB0)
00	3	10	Reg1,Reg2	ADB Rd,Rs
01	3	10	Reg1,Reg2	SBB Rd,Rs
02	3	10	Reg1,Reg2	AD Rd,Rs
03	3	10	Reg1,Reg2	SB Rd,Rs
04	3	10	Reg1,Reg2	AN Rd,Rs
05	3	10	Reg1,Reg2	NA Rd,Rs
06	3	10	Reg1,Reg2	OR Rd,Rs
07	3	10	Reg1,Reg2	XR Rd,Rs

; the destination register specified by the second operand byte (RB0)
; the source register specified by the third operand byte (RB1)
08	3	10	Reg1,Reg2	ADB Rd,Rs
09	3	10	Reg1,Reg2	SBB Rd,Rs
0A	3	10	Reg1,Reg2	AD Rd,Rs
0B	3	10	Reg1,Reg2	SB Rd,Rs
0C	3	10	Reg1,Reg2	AN Rd,Rs
0D	3	10	Reg1,Reg2	NA Rd,Rs
0E	3	10	Reg1,Reg2	OR Rd,Rs
0F	3	10	Reg1,Reg2	XR Rd,Rs

; first source register Rsf specified by the second operand byte (RB0)
; last destination register Rdl specified by the third operand byte (RB1)
10	3	6+4*i	Reg1,Reg3	ADBM Rdf..Rdl,Rsf..Rsl
11	3	6+4*i	Reg1,Reg3	SBBM Rdf..Rdl,Rsf..Rsl
12	3	6+4*i	Reg1,Reg3	ADM Rdf..Rdl,Rsf..Rsl
13	3	6+4*i	Reg1,Reg3	SBM Rdf..Rdl,Rsf..Rsl
14	3	6+4*i	Reg1,Reg3	ANM Rdf..Rdl,Rsf..Rsl
15	3	6+4*i	Reg1,Reg3	NAM Rdf..Rdl,Rsf..Rsl
16	3	6+4*i	Reg1,Reg3	ORM Rdf..Rdl,Rsf..Rsl
17	3	6+4*i	Reg1,Reg3	XRM Rdf..Rdl,Rsf..Rsl

; first destination register Rdf specified by the second operand byte (RB0)
; last source register Rsl specified by the third operand byte (RB1)
18	3	6+4*i	Reg1,Reg3	ADBM Rdf..Rdl,Rsf..Rsl
19	3	6+4*i	Reg1,Reg3	SBBM Rdf..Rdl,Rsf..Rsl
1A	3	6+4*i	Reg1,Reg3	ADM Rdf..Rdl,Rsf..Rsl
1B	3	6+4*i	Reg1,Reg3	SBM Rdf..Rdl,Rsf..Rsl
1C	3	6+4*i	Reg1,Reg3	ANM Rdf..Rdl,Rsf..Rsl
1D	3	6+4*i	Reg1,Reg3	NAM Rdf..Rdl,Rsf..Rsl
1E	3	6+4*i	Reg1,Reg3	ORM Rdf..Rdl,Rsf..Rsl
1F	3	6+4*i	Reg1,Reg3	XRM Rdf..Rdl,Rsf..Rsl

; the destination register specified by the third operand byte (RB1)
; the source register specified by the second operand byte (RB0)
20	3	10	Reg1,Reg2	TADB Rd,Rs
21	3	10	Reg1,Reg2	TSBB Rd,Rs
22	3	10	Reg1,Reg2	TAD Rd,Rs
23	3	10	Reg1,Reg2	TSB Rd,Rs
24	3	10	Reg1,Reg2	TAN Rd,Rs
25	3	10	Reg1,Reg2	TNA Rd,Rs
26	3	10	Reg1,Reg2	TOR Rd,Rs
27	3	10	Reg1,Reg2	TXR Rd,Rs

; the destination register specified by the second operand byte (RB0)
; the source register specified by the third operand byte (RB1)
28	3	10	Reg1,Reg2	TADB Rd,Rs
29	3	10	Reg1,Reg2	TSBB Rd,Rs
2A	3	10	Reg1,Reg2	TAD Rd,Rs
2B	3	10	Reg1,Reg2	TSB Rd,Rs
2C	3	10	Reg1,Reg2	TAN Rd,Rs
2D	3	10	Reg1,Reg2	TNA Rd,Rs
2E	3	10	Reg1,Reg2	TOR Rd,Rs
2F	3	10	Reg1,Reg2	TXR Rd,Rs

; first source register Rsf specified by the second operand byte (RB0)
; last destination register Rdl specified by the third operand byte (RB1)
30	3	6+4*i	Reg1,Reg3	TADBM Rdf..Rdl,Rsf..Rsl
31	3	6+4*i	Reg1,Reg3	TSBBM Rdf..Rdl,Rsf..Rsl
32	3	6+4*i	Reg1,Reg3	TADM Rdf..Rdl,Rsf..Rsl
33	3	6+4*i	Reg1,Reg3	TSBM Rdf..Rdl,Rsf..Rsl
34	3	6+4*i	Reg1,Reg3	TANM Rdf..Rdl,Rsf..Rsl
35	3	6+4*i	Reg1,Reg3	TNAM Rdf..Rdl,Rsf..Rsl
36	3	6+4*i	Reg1,Reg3	TORM Rdf..Rdl,Rsf..Rsl
37	3	6+4*i	Reg1,Reg3	TXRM Rdf..Rdl,Rsf..Rsl

; first destination register Rdf specified by the second operand byte (RB0)
; last source register Rsl specified by the third operand byte (RB1)
38	3	6+4*i	Reg1,Reg3	TADBM Rdf..Rdl,Rsf..Rsl
39	3	6+4*i	Reg1,Reg3	TSBBM Rdf..Rdl,Rsf..Rsl
3A	3	6+4*i	Reg1,Reg3	TADM Rdf..Rdl,Rsf..Rsl
3B	3	6+4*i	Reg1,Reg3	TSBM Rdf..Rdl,Rsf..Rsl
3C	3	6+4*i	Reg1,Reg3	TANM Rdf..Rdl,Rsf..Rsl
3D	3	6+4*i	Reg1,Reg3	TNAM Rdf..Rdl,Rsf..Rsl
3E	3	6+4*i	Reg1,Reg3	TORM Rdf..Rdl,Rsf..Rsl
3F	3	6+4*i	Reg1,Reg3	TXRM Rdf..Rdl,Rsf..Rsl

; the low order register specified by the second operand byte
; the high order register specified by the third operand byte
50	3	12	Reg1,Reg2	IJMP 16-bit-register
51..57	3	10/12	Reg1,Reg2	IJMP cc,16-bit-register
59..5F	3	10/12	Reg1,Reg2	IJMP cc,16-bit-register

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rs belongs to RB0
; bit 3 cleared	-> Rs belongs to RB1
80/88	2	16	Reg1		ST +(IX),Rs
81/89	2	16	Reg1		ST +(IY),Rs
82/8A	2	16	Reg1		ST +(IZ),Rs
83/8B	2	16	Reg1		ST +(SP),Rs
84/8C	2	16	Reg1		ST -(IX),Rs
85/8D	2	16	Reg1		ST -(IY),Rs
86/8E	2	16	Reg1		ST -(IZ),Rs
87/8F	2	16	Reg1		ST -(SP),Rs

; first source register Rsf specified by the second operand byte
; bits 2..0 of the last source register Rsl specified by the third operand
; byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rsf..Rsl belong to RB0
; bit 3 cleared	-> Rsf..Rsl belong to RB1
90/98	3	14+4*i	Reg1,Reg3	STM +(IX),Rsf..Rsl
91/99	3	14+4*i	Reg1,Reg3	STM +(IY),Rsf..Rsl
92/9A	3	14+4*i	Reg1,Reg3	STM +(IZ),Rsf..Rsl
93/9B	3	14+4*i	Reg1,Reg3	STM +(SP),Rsf..Rsl
94/9C	3	14+4*i	Reg1,Reg3	STM -(IX),Rsf..Rsl
95/9D	3	14+4*i	Reg1,Reg3	STM -(IY),Rsf..Rsl
96/9E	3	14+4*i	Reg1,Reg3	STM -(IZ),Rsf..Rsl
97/9F	3	14+4*i	Reg1,Reg3	STM -(SP),Rsf..Rsl

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
A0/A8	2	16	Reg1		LD Rd,(IX)+
A1/A9	2	16	Reg1		LD Rd,(IY)+
A2/AA	2	16	Reg1		LD Rd,(IZ)+
A3/AB	2	16	Reg1		LD Rd,(SP)+
A4/AC	2	16	Reg1		LD Rd,(IX)-
A5/AD	2	16	Reg1		LD Rd,(IY)-
A6/AE	2	16	Reg1		LD Rd,(IZ)-
A7/AF	2	16	Reg1		LD Rd,(SP)-

; first destination register Rdf specified by the second operand byte
; bits 2..0 of the last destination register Rdl specified by the third
; operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
B0/B8	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IX)+
B1/B9	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IY)+
B2/BA	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IZ)+
B3/BB	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(SP)+
B4/BC	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IX)-
B5/BD	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IY)-
B6/BE	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IZ)-
B7/BF	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(SP)-

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rs belongs to RB0
; bit 3 cleared	-> Rs belongs to RB1
C4/CC	2	8	Reg1		PST KO,Rs	;Keyboard Output Port
C5/CD	2	8	Reg1		PST F,Rs	;Flags
C6/CE	2	8	Reg1		PST AS,Rs	;Addres Select
C7/CF	2	8	Reg1		PST IE,Rs	;Interrupt Enable

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
D4/DC	2	8	Reg1		GST Rd,KO	;Keyboard Output Port
D5/DD	2	8	Reg1		GST Rd,F	;Flags
D6/DE	2	8	Reg1		GST Rd,AS	;Addres Select
D7/DF	2	8	Reg1		GST Rd,IE	;Interrupt Enable

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
E0/E8	2	8	Reg1		CMP Rd
E4/EC	2	8	Reg1		CMPB Rd
E6/EE	2	8	Reg1		ROU Rd
F0/F8	2	8	Reg1		INV Rd
F6/FE	2	8	Reg1		ROD Rd

; first destination register Rdf specified by the second operand byte
; bits 2..0 of the last destination register Rdl specified by the third
; operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
F4/FC	3	6+4*i	Reg1,Reg3	CMPBM Rdf..Rdl

; last destination register Rdl specified by the third operand byte
; bits 2..0 of the first destination register Rdf specified by the second
; operand byte
; Rdf..Rdl belong to RB1
E1	3	6+4*i	Reg1,Reg3	CMPM Rdf..Rdl
E3	3	6+4*i	Reg1,Reg3	BYUM Rdf..Rdl
E5	3	6+4*i	Reg1,Reg3	DIUM Rdf..Rdl
E7	3	6+4*i	Reg1,Reg3	ROUM Rdf..Rdl
F1	3	6+4*i	Reg1,Reg3	INVM Rdf..Rdl
F3	3	6+4*i	Reg1,Reg3	BYDM Rdf..Rdl
F5	3	6+4*i	Reg1,Reg3	DIDM Rdf..Rdl
F7	3	6+4*i	Reg1,Reg3	RODM Rdf..Rdl

; first destination register Rdf specified by the second operand byte
; bits 2..0 of the last destination register Rdl specified by the third
; operand byte
; Rdf..Rdl belong to RB0
E9	3	6+4*i	Reg1,Reg3	CMPM Rdf..Rdl
EB	3	6+4*i	Reg1,Reg3	BYUM Rdf..Rdl
ED	3	6+4*i	Reg1,Reg3	DIUM Rdf..Rdl
EF	3	6+4*i	Reg1,Reg3	ROUM Rdf..Rdl
F9	3	6+4*i	Reg1,Reg3	INVM Rdf..Rdl
FB	3	6+4*i	Reg1,Reg3	BYDM Rdf..Rdl
FD	3	6+4*i	Reg1,Reg3	DIDM Rdf..Rdl
FF	3	6+4*i	Reg1,Reg3	RODM Rdf..Rdl


Instructions selected by set bit 7 of the second byte
-----------------------------------------------------

; the destination register specified by the second operand byte
; the immediate data specified by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
00/08	3	10	Reg1,Im8	ADB Rd,nn
01/09	3	10	Reg1,Im8	SBB Rd,nn
02/0A	3	10	Reg1,Im8	AD Rd,nn
03/0B	3	10	Reg1,Im8	SB Rd,nn
04/0C	3	10	Reg1,Im8	AN Rd,nn
05/0D	3	10	Reg1,Im8	NA Rd,nn
06/0E	3	10	Reg1,Im8	OR Rd,nn
07/0F	3	10	Reg1,Im8	XR Rd,nn

; first destination register Rdf and bit 5 of the immediate data specified
; by the second operand byte
; bits 2..0 of the last destination register Rdl and bits 4..0 of the
; the immediate data specified by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
10/18	3	6+4*i	Reg1,Im6	ADBM Rdf..Rdl,nn
11/19	3	6+4*i	Reg1,Im6	SBBM Rdf..Rdl,nn
12/1A	3	6+4*i	Reg1,Im6	ADM Rdf..Rdl,nn
13/1B	3	6+4*i	Reg1,Im6	SBM Rdf..Rdl,nn

; the source register specified by the second operand byte (RB0)
; the destination register specified by the third operand byte (RB1)
14	3	10	Reg1,Reg2	SWP Rd,Rs
16	3	10	Reg1,Reg2	XCLS Rd,Rs
1C	3	10	Reg1,Reg2	XC Rd,Rs
1E	3	10	Reg1,Reg2	XCHS Rd,Rs

; first source register Rsf specified by the second operand byte (RB0)
; last destination register Rdl specified by the third operand byte (RB1)
15	3	6+4*i	Reg1,Reg3	SWPM Rdf..Rdl,Rsf..Rsl
17	3	6+4*i	Reg1,Reg3	XCLSM Rdf..Rdl,Rsf..Rsl
1D	3	6+4*i	Reg1,Reg3	XCM Rdf..Rdl,Rsf..Rsl
1F	3	6+4*i	Reg1,Reg3	XCHSM Rdf..Rdl,Rsf..Rsl

; the destination register specified by the second operand byte
; the immediate data specified by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
20/28	3	10	Reg1,Im8	TADB Rd,nn
21/29	3	10	Reg1,Im8	TSBB Rd,nn
22/2A	3	10	Reg1,Im8	TAD Rd,nn
23/2B	3	10	Reg1,Im8	TSB Rd,nn
24/2C	3	10	Reg1,Im8	TAN Rd,nn
25/2D	3	10	Reg1,Im8	TNA Rd,nn
26/2E	3	10	Reg1,Im8	TOR Rd,nn
27/2F	3	10	Reg1,Im8	TXR Rd,nn

; first destination register Rdf and bit 5 of the immediate data specified
; by the second operand byte
; last destination register Rdl and bits 4..0 of the immediate data specified
; by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
30/38	3	6+4*i	Reg1,Im6	TADBM Rdf..Rdl,nn
31/39	3	6+4*i	Reg1,Im6	TSBBM Rdf..Rdl,nn
32/3A	3	6+4*i	Reg1,Im6	TADM Rdf..Rdl,nn
33/3B	3	6+4*i	Reg1,Im6	TSBM Rdf..Rdl,nn

34	2	14*i	?		block search +(IX),?
35	2	14*i	?		block search +(IY),?
36	2	14*i	?		block search +(IZ),?
37	2	14*i	?		block search +(SP),?

3C	2	14*i	?		block search -(IX),?
3D	2	14*i	?		block search -(IY),?
3E	2	14*i	?		block search -(IZ),?
3F	2	14*i	?		block search -(SP),?

50	2	6	-		OFF

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
51/59	2	8	Reg1		GST Rd,KI	;Keyboard Input Port
F1/F9	2	8	Reg1		GST Rd,IF	;Interrupt Flags

; the destination register specified by the second operand byte
; the immediate data specified by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
52/5A	3	10	Reg1,Im8	BIT Rd,nn
56/5E	3	10	Reg1,Im8	LD Rd,nn

; the source register specified by the second operand byte (RB0)
; the destination register specified by the third operand byte (RB1)
53	3	10	Reg1,Reg2	BIT Rd,Rs
54	3	10	Reg1,Reg2	LD Rd,Rs

; first source register Rsf specified by the second operand byte (RB0)
; last destination register Rdl specified by the third operand byte (RB1)
55	3	6+4*i	Reg1,Reg3	LDM Rdf..Rdl,Rsf..Rsl

; first destination register Rdf and bit 5 of the immediate data specified
; by the second operand byte
; last destination register Rdl and bits 4..0 of the immediate data specified
; by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
57/5F	3	6+4*i	Reg1,Im6	LDM Rdf..Rdl,nn

; the destination register specified by the second operand byte (RB0)
; the source register specified by the third operand byte (RB1)
5B	3	10	Reg1,Reg2	BIT Rd,Rs
5C	3	10	Reg1,Reg2	LD Rd,Rs

; first destination register Rdf specified by the second operand byte (RB0)
; last source register Rsl specified by the third operand byte (RB1)
5D	3	6+4*i	Reg1,Reg3	LDM Rdf..Rdl,Rsf..Rsl

; the index register specified by the second operand byte (RB0)
; the source register specified by the third operand byte (RB1)
80	3	18	Reg1,Reg2	ST (IX+Ri),Rs
81	3	18	Reg1,Reg2	ST (IY+Ri),Rs
82	3	18	Reg1,Reg2	ST (IZ+Ri),Rs
83	3	18	Reg1,Reg2	ST (SP+Ri),Rs
84	3	18	Reg1,Reg2	ST (IX-Ri),Rs
85	3	18	Reg1,Reg2	ST (IY-Ri),Rs
86	3	18	Reg1,Reg2	ST (IZ-Ri),Rs
87	3	18	Reg1,Reg2	ST (SP-Ri),Rs

; the source register specified by the second operand byte (RB0)
; the immediate index specified by the third operand byte
88	3	18	Reg1,Im8	ST (IX+nn),Rs
89	3	18	Reg1,Im8	ST (IY+nn),Rs
8A	3	18	Reg1,Im8	ST (IZ+nn),Rs
8B	3	18	Reg1,Im8	ST (SP+nn),Rs
8C	3	18	Reg1,Im8	ST (IX-nn),Rs
8D	3	18	Reg1,Im8	ST (IY-nn),Rs
8E	3	18	Reg1,Im8	ST (IZ-nn),Rs
8F	3	18	Reg1,Im8	ST (SP-nn),Rs

; the index register specified by the second operand byte (RB0)
; last source register Rsl specified by the third operand byte
; first source register Rsf specified by bits 2..0 of the second operand byte
; the source register array belongs to RB1
90	3	14+4*i	Reg1,Reg3	STM (IX+Ri),Rsf..Rsl
91	3	14+4*i	Reg1,Reg3	STM (IY+Ri),Rsf..Rsl
92	3	14+4*i	Reg1,Reg3	STM (IZ+Ri),Rsf..Rsl
93	3	14+4*i	Reg1,Reg3	STM (SP+Ri),Rsf..Rsl
94	3	14+4*i	Reg1,Reg3	STM (IX-Ri),Rsf..Rsl
95	3	14+4*i	Reg1,Reg3	STM (IY-Ri),Rsf..Rsl
96	3	14+4*i	Reg1,Reg3	STM (IZ-Ri),Rsf..Rsl
97	3	14+4*i	Reg1,Reg3	STM (SP-Ri),Rsf..Rsl

; first source register Rsf and bit 5 of the immediate index specified by
; the second operand byte
; last source register Rsl and bits 4..0 of the immediate index specified by
; the third operand byte
; the source register array belongs to RB0
98	3	14+4*i	Reg1,Im6	STM (IX+nn),Rsf..Rsl
99	3	14+4*i	Reg1,Im6	STM (IY+nn),Rsf..Rsl
9A	3	14+4*i	Reg1,Im6	STM (IZ+nn),Rsf..Rsl
9B	3	14+4*i	Reg1,Im6	STM (SP+nn),Rsf..Rsl
9C	3	14+4*i	Reg1,Im6	STM (IX-nn),Rsf..Rsl
9D	3	14+4*i	Reg1,Im6	STM (IY-nn),Rsf..Rsl
9E	3	14+4*i	Reg1,Im6	STM (IZ-nn),Rsf..Rsl
9F	3	14+4*i	Reg1,Im6	STM (SP-nn),Rsf..Rsl

; the index register specified by the second operand byte (RB0)
; the destination register specified by the third operand byte (RB1)
A0	3	18	Reg1,Reg2	LD Rd,(IX+Ri)
A1	3	18	Reg1,Reg2	LD Rd,(IY+Ri)
A2	3	18	Reg1,Reg2	LD Rd,(IZ+Ri)
A3	3	18	Reg1,Reg2	LD Rd,(SP+Ri)
A4	3	18	Reg1,Reg2	LD Rd,(IX-Ri)
A5	3	18	Reg1,Reg2	LD Rd,(IY-Ri)
A6	3	18	Reg1,Reg2	LD Rd,(IZ-Ri)
A7	3	18	Reg1,Reg2	LD Rd,(SP-Ri)

; the destination register specified by the second operand byte (RB0)
; the immediate index specified by the third operand byte
A8	3	18	Reg1,Im8	LD Rd,(IX+nn)
A9	3	18	Reg1,Im8	LD Rd,(IY+nn)
AA	3	18	Reg1,Im8	LD Rd,(IZ+nn)
AB	3	18	Reg1,Im8	LD Rd,(SP+nn)
AC	3	18	Reg1,Im8	LD Rd,(IX-nn)
AD	3	18	Reg1,Im8	LD Rd,(IY-nn)
AE	3	18	Reg1,Im8	LD Rd,(IZ-nn)
AF	3	18	Reg1,Im8	LD Rd,(SP-nn)

; the index register specified by the second operand byte (RB0)
; last destination register Rdl specified by the third operand byte
; first destination register Rdf specified by bits 2..0 of the second operand
; byte
; the destination register array belongs to RB1
B0	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IX+Ri)
B1	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IY+Ri)
B2	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IZ+Ri)
B3	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(SP+Ri)
B4	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IX-Ri)
B5	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IY-Ri)
B6	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(IZ-Ri)
B7	3	14+4*i	Reg1,Reg3	LDM Rdf..Rdl,(SP-Ri)

; first destination register Rdf and bit 5 of the immediate index specified
; by the second operand byte
; last destination register Rdl and bits 4..0 of the immediate index
; specified by the third operand byte
; the destination register array belongs to RB0
B8	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IX+nn)
B9	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IY+nn)
BA	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IZ+nn)
BB	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(SP+nn)
BC	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IX-nn)
BD	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IY-nn)
BE	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(IZ-nn)
BF	3	14+4*i	Reg1,Im6	LDM Rdf..Rdl,(SP-nn)

; the data register specified by the second operand byte
; the immediate data specified by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> data register belongs to RB0
; bit 3 cleared	-> data register belongs to RB1
C4/CC	3	16	Reg1,Im8	LDLE Rd,nn
C5/CD	3	16	Reg1,Im8	LDLO Rd,nn
C6/CE	3	16	Reg1,Im8	STLE Rs,nn
C7/CF	3	16	Reg1,Im8	STLO Rs,nn

; first destination register Rdf and bit 5 of the immediate data specified
; by the second operand byte
; last destination register Rdl and bits 4..0 of the immediate data specified
; by the third operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> registers belong to RB0
; bit 3 cleared	-> registers belong to RB1
D4/DC	3	8+8*i	Reg1,Im6	LDLEM Rdf..Rdl,nn
D5/DD	3	8+8*i	Reg1,Im6	LDLOM Rdf..Rdl,nn
D6/DE	3	8+8*i	Reg1,Im6	STLEM Rsf..Rsl,nn
D7/DF	3	8+8*i	Reg1,Im6	STLOM Rsf..Rsl,nn

; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rd belongs to RB0
; bit 3 cleared	-> Rd belongs to RB1
E0/E8	2	8	Reg1		SWP Rd
E3/EB	2	8	Reg1		BYU Rd
E4/EC	2	8	Reg1		BIU Rd
E5/ED	2	8	Reg1		DIU Rd
E6/EE	2	8	Reg1		MTB Rd
F3/FB	2	8	Reg1		BYD Rd
F5/FD	2	8	Reg1		DID Rd

; last destination register Rdl specified by the third operand byte
; bits 2..0 of the first destination register Rdf specified by the second
; operand byte
; Rdf..Rdl belong to RB1
F0	3	6+4*i	Reg1,Reg3	BNUSM Rdf..Rdl
F4	3	6+4*i	Reg1,Reg3	BIUM Rdf..Rdl

; first destination register Rdf specified by the second operand byte
; bits 2..0 of the last destination register Rdl specified by the third
; operand byte
; register bank specified by the bit 3 of the first opcode byte:
; bit 3 set	-> Rdf..Rdl belong to RB0
; bit 3 cleared	-> Rdf..Rdl belong to RB1
F6/FE	3	6+4*i	Reg1,Reg3	MTBM Rdf..Rdl

; first destination register Rdf specified by the second operand byte
; bits 2..0 of the last destination register Rdl specified by the third
; operand byte
; Rdf..Rdl belong to RB0
F8	3	6+4*i	Reg1,Reg3	BNUSM Rdf..Rdl
FC	3	6+4*i	Reg1,Reg3	BIUM Rdf..Rdl

E7,EF,F7,FF
	2	16	-		TRP


Instructions independent on the bit 7 of the second byte
--------------------------------------------------------

40	3	10	Im16		LDW IX,nnnn
41	3	10	Im16		LDW IY,nnnn
42	3	10	Im16		LDW IZ,nnnn
43	3	10	Im16		LDW V3,nnnn
44	3	10	Im16		LDW V2,nnnn
45	3	10	Im16		LDW V1,nnnn
46	3	10	Im16		LDW V0,nnnn
47	3	10	Im16		LDW SP,nnnn

48	2	10	Im8		ADW IX,nn
49	2	10	Im8		ADW IY,nn
4A	2	10	Im8		ADW IZ,nn
4B	2	10	Im8		ADW SP,nn
4C	2	10	Im8		SBW IX,nn
4D	2	10	Im8		SBW IY,nn
4E	2	10	Im8		SBW IZ,nn
4F	2	10	Im8		SBW SP,nn

58	1	12	-		RTN

60..67	3	10/16	Im16		CAL cc,addr

68	1	6	-		CANI

69..6F	3	10/16	Im16		CAL cc,addr

70..77	3	10	Im16		JMP cc,addr

78	1	12	-		RTI

79..7F	3	10	Im16		JMP cc,addr

C0	2	8	Im8		PST KO,nn	;Keyboard Output Port
C1	2	8	Im8		PST IF,nn	;ENx Port Control
C2	2	8	Im8		PST AS,nn	;Addres Select
C3	2	8	Im8		PST IE,nn	;Interrupt Enable

C8	2	10	Im8		ST +(IX),nn
C9	2	10	Im8		ST +(IY),nn
CA	2	10	Im8		ST +(IZ),nn
CB	2	10	Im8		ST +(SP),nn

D0	2	10	Im8		ST (IX),nn
D1	2	10	Im8		ST (IY),nn
D2	2	10	Im8		ST (IZ),nn
D3	2	10	Im8		ST (SP),nn

D8	2	10	Im8		ST -(IX),nn
D9	2	10	Im8		ST -(IY),nn
DA	2	10	Im8		ST -(IZ),nn
DB	2	10	Im8		ST -(SP),nn

E2	1	14*i	-		BUP

F2	1	14*i	-		BDN

FA	1	6	-		NOP



Number of cycles
================

For the clock frequency of 910kHz the period of a cycle is 1.099us

The values are decimal, not hex.

The values apply for code stored in external memory. Execution time from
the microprocessor's internal ROM is shorter than in the 'fast' mode by
#opcode_bytes * 2 clock cycles, because accessing the internal ROM doesn't
consume any clock cycles.

i = size of the register array(s) or number of processed bytes

Two values are specified in following cases:
	call or jump not taken / call or jump taken



Operands
========

Reg1 = data register in range 00..3F

bits: ORRRIRRR

I = inverted most significant bit of an immediate 6-bit value, otherwise
    ignored

O = operation, extension of the first opcode byte

R = register, order of bits: *543*210

-----------------------------------------------------------------------------

Reg2 = data register in range 40..7F

bits: RRRKxRRR

R = register, order of bits: 210**543

K = 0: direct specification
    1: indirect specification with the contents of the AS register

x = should be cleared with 0

-----------------------------------------------------------------------------

Reg3 = register array

bits: LLLKxSSS

L = last register of the array(s), order of bits: 210*****
S = page of the second array (RB1), order of bits: *****543
K = 0: direct specification
    1: indirect specification with the contents of the AS register

x = should be cleared with 0

-----------------------------------------------------------------------------

Im6 = bits 4..0 of an immediate 6-bit value,
      last destination register of a register array

bits: RRRNNNNN

R = register, order of bits: 210*****

N = least significant bits of an immediate 6-bit value,
    order of bits: ***43210
    the most significant bit specified in the Reg1 type operand

-----------------------------------------------------------------------------

Im8 = immediate 8-bit value

-----------------------------------------------------------------------------

Im16 = immediate 16-bit value, the most significant byte first

-----------------------------------------------------------------------------

cc = Conditional Code

bits of the opcode: OOOOCCCC

O = operation code

C = conditional code, order of bits: ****3210
	0 = always (unconditional)
	1 = Key Pressed			9 = Key Not Pressed
	2 = Lower Zero			A = Not Lower Zero
	3 = Upper Zero			B = Not Upper Zero
	4 = Not Zero			C = Zero
	5 = Overflow			D = Not Overflow
	6 = Half Carry			E = Not Half Carry
	7 = Carry			F = Not Carry
