Description of the assembly language for following Casio microprocessors:
NM-325 / uPD1037 / HD62023
NM-326 / uPD3055 / HD62076

Most mnemonic names were adopted from the Casio's HD61700 official instruction
set.


The symbols listed below are used in the explanations and examples throughout
this document:

Rf..Rl		array of data registers
Sreg		status register
Im5		5-bit immediate data &H00..&H1F
Im7		7-bit immediate data &H00..&H7F
Im8		8-bit immediate data &H00..&HFF
Im16		16-bit immediate data &H0000..&HFFFF
<-		Transfer direction
&H		Prefix of a hexadecimal literal
( )		Contents of memory pointed to by the register included within
		parentheses



Memory Organization
===================

The microprocessor has separate address spaces for code (usually ROM), data
(usually RAM) and memory mapped control registers.

The address bus consists of 16 address lines A0..A15 controlled by the 16-bit
address registers (PC for code fetch, or IX, IY, IZ, SP when accessing data).
The NM-326 features additional 6 bank select lines RA14..RA19.

In the organizer SF-9350 the code memory is addressed by the lines A0..A14
and RA15..RA19 while the data memory by the lines A0..A15.



Internal registers
==================

The internal RAM is organized as 128 general purpose 8-bit registers divided
into two 64-byte banks RB0..RB1 and sixteen 8-byte pages RP0..RP15:

RB0 - registers R0..R63

RP0 - registers R0..R7
RP1 - registers R8..R15
RP2 - registers R16..R23
RP3 - registers R24..R31
RP4 - registers R32..R39
RP5 - registers R40..R47
RP6 - registers R48..R55
RP7 - registers R56..R63

RB1 - registers R64..R127

RP8 - registers R64..R71
RP9 - registers R72..R79
RP10 - registers R80..R87
RP11 - registers R88..R95
RP12 - registers R96..R103
RP13 - registers R104..R111
RP14 - registers R112..R119
RP15 - registers R120..R127

Up to 8 adjacent registers within the same page can be combined to handle up
to 64-bit data. The little-endian byte order is used (the least significant
first).

The registers in the bank RB0 can be accessed not only directly through their
absolute address, but also indirectly through the contents of the AS register.
Depending on the bit 0 of the AS register, only the lower 3 or all 6 bits of
the directly specified register address (index) are replaced with the contents
of the AS register.

Register notation:

 1. directly specified registers - letter 'R' followed by a decimal number in
  range 0..127

 2. indirectly specified registers (where part of the address is modified by
  the contents of the AS register) - letter 'I' followed by a decimal number
  in range 0..63

Registers R119..R127 (most significant byte) and R55..R63 (least significand
byte) form 9 special purpose 16-bit registers:
R119,R55 - trap vector
R120,R56 - index register IX
R121,R57 - index register IY
R122,R58 - index register IZ
R123,R59 - interrupt vector V3, address of the timer interrupt service routine
R124,R60 - interrupt vector V2, address of the INT2 service routine
R125,R61 - interrupt vector V1, address of the INT1 service routine
R126,R62 - interrupt vector V0, address of the INT0 service routine
R127,R63 - hardware stack pointer SP


F: Flag Register (8-bit, Read/Write)

	MSB     ->     LSB
	C H V Z UZ LZ * *

bit 7 - Carry Flag C, set to 1 when a carry or borrow occurs (C), and reset
 to 0 when a carry or borrow does not occur (NC).
bit 6 - Half Carry Flag H, set to 1 when a carry or borrow occurs from bit 3
 to bit 4 (H), and reset to 0 when a carry or borrow from bit 3 to bit 4 does
 not occur (NH).
bit 5 - Overflow Flag V, set to 1 when a carry or borrow occurs from bit 6
 to bit 7 (V), and reset to 0 when a carry or borrow from bit 6 to bit 7
 does not occur (NV). It can be used along with the Carry Flag to detect
 a two's-complement overflow condition as a result of an addition or
 a subtraction. The result of the operation is invalid when the V bit is set
 and the C bit is reset, or else when the V bit is reset and the C bit is set.
bit 4 - Zero Flag Z, set to 1 when all the bits of a calculation result are
 0 (Z), and reset to 0 when data are present (NZ).
bit 3 - Upper Digit Zero Flag UZ, set to 1 when the high-order 4 bits are 0
 due to a calculation result (UZ), and reset to 0 when data are present (NUZ).
bit 2 - Lower Digit Zero Flag LZ, set to 1 when the low-order 4 bits are 0
 due to a calculation result (LZ), and reset to 0 when data are present (NLZ).


KY: Keyboard Register (8-bit, Read/Write)

- when written, selects lines of the 12-bit KC output port

	KC11 - 1x1xxxxx		;x denote "don't care"
	KC10 - 1xx1xxxx
	KC9  - 1xxx1xxx
	KC8  - 1xxxx1xx
	KC7  - 1xxxxx1x
	KC6  - 1xxxxxx1
	KC5  - x11xxxxx
	KC4  - x1x1xxxx
	KC3  - x1xx1xxx
	KC2  - x1xxx1xx
	KC1  - x1xxxx1x
	KC0  - x1xxxxx1
	KAC  - 11xxxxxx or 01000000

- when read, returns the state of the 8-bit KI input port when the bit 7 or
  bit 6 of the data written to the KY register is set, otherwise retains the
  last captured value.
  The contents of the KY input register can be tested against zero with the
  conditional jump/call on K/NK. Note that the K/NK condition doesn't have
  any corresponding bit in the Flag Register.

  Example:
	    PST  KY,&H42	;select the key output KO2
	L1: SJMP NK,L1		;wait for a key to be pressed
	    PST  KY,&H00	;latch the keyboard input port state
	    GST  R1,KY		;read the captured keyboard input port state


IE: Interrupt Enable Register (8-bit, Read/Write)

bit 7 - global interrupt enable
bit 6 - INT2 terminal interrupt edge specification
	0: falling edge, 1: rising edge
bit 5 - INT1 terminal interrupt edge specification
	0: falling edge, 1: rising edge
bit 4 - INT0 terminal interrupt edge specification
	0: falling edge, 1: rising edge
bit 3 - timer interrupt enable
bit 2 - INT2 interrupt enable
bit 1 - INT1 interrupt enable
bit 0 - INT0 interrupt enable

The bit 7 needs to be set for the interrupts to be enabled. When an interrupt
condition occurs, an internal interrupt request latch is set, regardless of
the state of its corresponding enable bit. When this bit is set, the interrupt
gets serviced, otherwise the interrupt becomes pending.
Zero in the bit 7 causes all internal interrupt request and service latches to
be cleared.
All external interrupts INT0..INT2 have equal priority levels, unless there
exists some method to specify them (not found so far).
The timer interrupt has lower priority than the external interrupts.
An interrupt service routine of lower or equal priority can be always
interrupted by a higher priority interrupt.


PD: 8-bit Port Data Register (8-bit, Read/Write)


PE: 4-bit Port Data Register (7-bit, Write only)

bit 6 - sets the display memory scan direction
	1: the display memory pointer is incremented
	0: the display memory pointer is decremented 
bits 5..4 - function unknown
bit 3 - sets the state of the port pin L2
bit 2 - sets the state of the port pin L1
bit 1 - sets the state of the port pin H2 (inverted)
bit 0 - sets the state of the port pin H1 (inverted)


DS: Data Segment (8-bit, Read/Write)

bits 7,6 - probably unused
bits 5,4 - SP memory area specification
bits 3,2 - IY memory area specification
bits 1,0 - IX and IZ memory area specification

	00 - code memory (ROM)
	01 - unused
	10 - CPU control registers
	11 - data memory (RAM)


AS: Address Select (7-bit, Read/Write) - modifier of the register address
 allowing indirect access to the general purpose registers in the bank RB0.
 Order of bits: *543210M (M=mode)

 Indirect addressing to the register arrays is also possible. The indirectly
 specified array doesn't need to be aligned with the other one.

Options:

 1. When the bit 0 of the AS register is cleared, bits 6..1 form the address
  of the indirectly specified register in range R0..R63. The direct register
  address specified by the instruction opcode is ignored.
  bits: 0RRRRRR0

  Example how to clear registers R0 to R47 using indirect addressing
	    LD   R64,&H00
	    LD   R65,&H5E	;initialise the pointer to the register R47
	L1: PST  AS,R65		;set the pointer
	    LD   I0,R64		;write R64 to the register pointed to by AS
	    SB   R65,&H02	;decrement the pointer
	    SJMP NC,L1

  In this mode an indirectly specified array cannot wrap around. Reading an
  indirectly adressed register outside the page boundaries returns 0, writing
  has no effect.

  Examples:

  1.1 instruction LDM R66..R69,I42..I45

  AS=&H12: R66<-R9 R67<-R10 R68<-R11 R69<-R12	;the arrays don't need to be
						;aligned
  AS=&H1C: R66<-R14 R67<-R15 R68<-0 R69<-0	;crossed page boundary

  1.2 instruction DIUM I40..I43

  AS=&H26 - processed registers: R19, R20, R21, R22, because the page boundary
   wasn't crossed
  AS=&H2A - processed registers: R21, R22, R23 and a dummy virtual register
   outside the page boundary containing &H00

  1.3 instruction DIDM I43..I40

  AS=&H4C - processed registers: R38, R37, R36, R35, because the page boundary
   wasn't crossed
  AS=&H44 - processed registers: R34, R33, R32 and a dummy virtual register
   outside the page boundary, containing &H00

 2. When the bit 0 of the AS register is set, only bits 3..1 thereof modify
  the bits 2..0 of the address of the indirectly specified register. The bits
  5..3 of the address remain as set by the instruction opcode.
  bits: 0xxxRRR1 (x=ignored)

  Example:
	    PST AS,&H07
	    LD  R69,I40		;the contents of the register R43 will be
				;transferred to the register R69

  In case of an indirectly specified array, bits 3..1 specify the first
  register of the array, while bits 6..4 specify the last register of the
  array. For instructions which process registers downwards (BYDM, DIDM, RODM)
  the bits 6..4 are inverted.
  Reading an indirectly addressed register after the last one returns 0,
  writing has no effect.
  bits: 0LLLFFF1

  Examples:

  2.1 instruction LDM R66..R69,I42..I45

  AS=&H77: R66<-R43 R67<-R44 R68<-R45 R69<-R46	;last indirectly specified
						;register = R47, the arrays
						;don't need to be aligned
  AS=&H47: R66<-R43 R67<-R44 R68<-0 R69<-0	;last indirectly specified
						;register = R44
  AS=&H5D: R66<-R46 R67<-R47 R68<-R40 R69<-R41	;last indirectly specified
						;register = R45, wrapping
						;around is supported

  2.2 instruction LDM I42..I45,R66..R69

  AS=&H47: R43<-R66 R44<-R67 void<-R68 void<-R69 ;last indirectly specified
						;register = R44

  2.3 instruction DIUM I40..I43

  AS=&H75 - processed registers: R42, R43, R44, R45, last indirectly specified
   register = R47
  AS=&H45 - processed registers: R42, R43, R44 and a dummy virtual register
   containing &H00, because R44 was indirectly specified as the last one
  AS=&H5D - processed registers: R46, R47, R40, R41, last indirectly specified
   register = R45, wrapping around is supported

  2.4 instruction DIDM I43..I40

  AS=&H79 - processed registers: R44, R43, R42, R41, last indirectly specified
   register = R40
  AS=&H59 - processed registers: R44, R43, R42 and a dummy virtual register
   containing &H00, because R42 was indirectly specified as the last one
  AS=&H53 - processed registers: R41, R40, R47, R46, last indirectly specified
   register = R42, wrapping around is supported


Registers related to the integrated display controller
======================================================

LA: display memory address (16-bit, write only)

  The display memory pointer is initialised to the address LA, and
  predecremented or preincremented (depending on the bit 6 of the register PE)
  during the data transfer.


S5: display clock divisor (7-bit, write only)

  display_line_frequency = osc_frequency / prescaler / S5
  frame_rate = display_line_frequency / number_of_lines


S7: display width (7-bit, write only)

  horizontal_resolution = 8 * (S7 + 1)


S6: display height and control (7-bit, write only)

bits 6..4 - display clock prescaler
	111: divide by 16
  Other values may be incorrectly implemented, because for them the total
  division rate appears to be calculated as follows: (prescaler * S5) mod 256
	010: divide by 600
	011: divide by 40
	100: divide by 40
	101: divide by 240
	110: divide by 80
bits 3..1 - specify vertical resolution in 16-pixel units
bit 0 - mode selection
	0: LCD driver configuration (output PRO=0)
	1: data transfer (output PRO=1)


TM: Timer Divisor (7-bit, write only)

  timer_interrupt_rate = display_line_frequency / TM

  If TM = 0 then the timer is stopped.


Example from an SF-9350 organizer with a screen resolution of 192x48 pixels:

	PST S5,&H2F	;display line frequency = 2010kHz / 16 / &H2F = 2673Hz
			;display frame rate = 2673Hz / 48 lines = 56Hz
	PST S7,&H17	;horizontal resolution = 8 * (&H17 + 1) = 192 pixels
	PST S6,&H77	;vertical resolution 011 = 16 * 3 = 48 pixels
			;display clock prescaler 111 = divide by 16


CPU control registers (applies to the NM-326 processor)
=======================================================

&H8002 - specification of the memory bank for code execution
bits 5..0 are output to the RA19..RA14 pins for the PC address in range
 &H8000..&HFFFF

 Code in the address range &H0000..&H7FFF is always executed from bank 0,
 i.e. the RA19..RA14 pins are at low logical level.

 Example for an SF-9350 organizer:

 ;code placed in the address range &H0000..&H7FFF
	PST	DS,&HFB		;IY points to the CPU control registers
	LDW	IY,&H8001
	LD	R0,&H0C
	ST	(IY+1),R0
	CAL	&H9ABC		;effective code memory address &H31ABC
	LD	R0,&H16
	ST	(IY+1),R0
	CAL	&HDEF0		;effective code memory address &H5DEF0
	...


&H8008, &H8009 - specification of the memory bank for data access
bits 7..5 must be cleared
bits 4..0 are output on the RA19..RA15 pins when data are read/written to
 memory, but not when an instruction is fetched. For an address in range
 &H0000..&H7FFF the value written to the register &H8008 is used. For an
 address in range &H8000..&HFFFF the value written to the register &H8009
 is used.

 Example for an SF-9350 organizer:

	PST	DS,&HFB		;IY points to the CPU control registers
	LDW	IY,&H8007
	LD	R0,&H05
	LD	R1,&H02
	STM	+(IY),R0..R1
	PST	DS,&HF3		;IY points to the code memory
	LDW	IY,&H5678
	LD	R2,(IY)+	;effective code memory address &H2D678
	LDW	IY,&HECDB
	LD	R3,(IY)+	;effective code memory address &H16CDB


&HE000
bit 7 - selects between the slow/fast memory access mode, i.e. specifies the
 number of clock cycles required for a memory access
 - three clock cycles when cleared (SF-8xxx, SF-9xxx operating mode)
 - two clock cycles when set (SF-R10, SF-R20 operating mode)
 The NM-325 CPU operates in the fast mode.
bits 6..0 - cleared, function unknown 


Instruction syntax
==================

Example mnemonic name: TADBCM
T - test mode, the result of operation isn't stored
AD - addition
B - decimal mode (BCD)
C - with Carry
M - multibyte

Order of operands: destination, source


Instruction set
===============

Mnemonic:	AD (Add)
Syntax:		AD dst,src
Execution:	dst <- dst + src
Description:	Adds the source to the destination and stores the result in
		the destination.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		AD Rd,Rs	;the source and destination register must
				;belong to different register banks
		AD Rd,Im8
		AD (IX),Rs
		AD (IY),Rs
		AD (IX),Im8
		AD (IY),Im8
Examples:
		AD R10,R70
		AD R80,R20
		AD I25,R88
		AD R99,I44
		AD R16,&H55
		AD (IX),R110
		AD (IY),R47
		AD (IX),&HFE
		AD (IY),&H6A

--------------------

Mnemonic:	ADB (Add BCD)
Syntax:		ADB dst,src
Execution:	dst <- dst + src, produces a decimal result
Description:	Adds the source to the destination, and stores the result in
		the destination. Each byte is assumed to contain two digits
		in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADB Rd,Rs	;the source and destination register must
				;belong to different register banks
		ADB Rd,Im8
		ADB (IX),Rs
		ADB (IY),Rs
		ADB (IX),Im8
		ADB (IY),Im8
Examples:
		ADB R10,R70
		ADB R80,R20
		ADB I25,R88
		ADB R99,I44
		ADB R16,&H55
		ADB (IX),R110
		ADB (IY),R47
		ADB (IX),&HFE
		ADB (IY),&H6A

--------------------

Mnemonic:	ADBC (Add BCD With Carry)
Syntax:		ADBC dst,src
Execution:	dst <- dst + src + Carry, produces decimal result
Description:	Adds the source, the destination and the carry bit and stores
		the result in the destination. Each byte is assumed to contain
		two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		ADBC Rd,Im8
Examples:
		ADBC R10,R70
		ADBC R80,R20
		ADBC I25,R88
		ADBC R99,I44
		ADBC R16,&H55

--------------------

Mnemonic:	ADBCM (Add BCD With Carry Multibyte)
Syntax:		ADBCM dst,src
Execution:	dst <- dst + src + Carry, produces decimal result
Description:	Adds the source and the carry bit to the destination array,
		and stores the result in the destination array. Each byte is
		assumed to contain two digits in binary-coded decimal (BCD)
		form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADBCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		ADBCM R1..R3,R65..R67
		ADBCM I24..I31,R96..R103
		ADBCM R66..R67,I58..I59
		ADBCM R10..R13,&H15

--------------------

Mnemonic:	ADBM (Add BCD Multibyte)
Syntax:		ADBM dst,src
Execution:	dst <- dst + src, produces a decimal result
Description:	Adds the source to the destination array, and stores the
		result in the destination array. Each byte is assumed to
		contain two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		ADBM R0..R3,R64..R67
		ADBM I24..I31,R96..R103
		ADBM R66..R67,I58..I59
		ADBM R73..R76,&H05

--------------------

Mnemonic:	ADC (Add With Carry)
Syntax:		ADC dst,src
Execution:	dst <- dst + src + Carry
Description:	Adds the source, the destination and the carry bit and stores
		the result in the destination.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADC Rd,Rs	;the source and destination register must
				;belong to different register banks
		ADC Rd,Im8
Examples:
		ADC R10,R70
		ADC R80,R20
		ADC I25,R88
		ADC R99,I44
		ADC R16,&H55

--------------------

Mnemonic:	ADCM (Add With Carry Multibyte)
Syntax:		ADCM dst,src
Execution:	dst <- dst + src + Carry
Description:	Adds the source and the carry bit to the destination array,
		and stores the result in the destination array.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		ADCM R80..R86,R16..R22
		ADCM I24..I31,R96..R103
		ADCM R66..R67,I58..I59
		ADCM R10..R15,&H0D

--------------------

Mnemonic:	ADM (Add Multibyte)
Syntax:		ADM dst,src
Execution:	dst <- dst + src
Description:	Adds the source to the destination array and stores the result
		in the destination array.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		ADM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		ADM Rdf..Rdl,Im5	;immediate 5-bit operand
Example:
		ADM R100..R103,R44..R47
		ADM I24..I31,R96..R103
		ADM R76..R79,I44..I47
		ADM R24..R31,&H1C

--------------------

Mnemonic:	ADW (Add Word)
Syntax:		ADW dst,src
Execution:	dst <- dst + src
Description:	Adds the source to the destination, and stores the result in
		the destination.
Flags:		none affected
Options:
		ADW IX,Im7
		ADW IY,Im7
		ADW IZ,Im7
		ADW SP,Im7

		ADW IX,Rs	;8-bit contents of a single data register
		ADW IY,Rs
		ADW IZ,Rs
		ADW SP,Rs
Examples:
		ADW IX,&H5A		;IX <- IX + &H5A
		ADW SP,R6		;SP <- SP + R6

--------------------

Mnemonic:	AN (Logical AND)
Syntax:		AN dst,src
Execution:	dst <- dst AND src
Description:	Logically ANDs the source and the destination and stores the
		result in the destination.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Options:
		AN Rd,Rs	;the source and destination register must
				;belong to different register banks
		AN Rd,Im8
		AN (IX),Rs
		AN (IY),Rs
		AN (IX),Im8
		AN (IY),Im8
Examples:
		AN R10,R70
		AN R80,R20
		AN I25,R101
		AN R99,I44
		AN R16,&H55
		AN (IX),R110
		AN (IY),R47
		AN (IX),&HFE
		AN (IY),&H6A

--------------------

Mnemonic:	ANM (Logical AND Multibyte)
Syntax:		ANM dst,src
Execution:	dst <- dst AND src
Description:	Logically ANDs two register arrays and stores the result in
		the destination array. Both register arrays must belong to
		different register banks.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		ANM R0..R7,R64..R71
		ANM R83..R87,R51..R55
		ANM I33..I34,R81..R82
		ANM R109..R111,I45..I47

--------------------

Mnemonic:	BDN (Block Down)
Syntax:		BDN Reg
Execution:
		+->  IX <- IX - 1
		|    IY <- IY - 1
		|    (IY) <- (IX)
		|    Reg <- Reg - 1
		+--  repeat if Reg <> 0

Description:	Copies a block of memory where:
		IX-register = original block beginning address + 1
		IY-register = destination beginning address + 1
		Reg = number of transferred bytes
		The interrupts can be serviced during the transfer.
Flags:		none affected
Example:
		LD R5,&H28
		LDW IX,&H2000
		LDW IY,&H4000
		BDN R5
		; the memory block &H1FD8-&H1FFF will be copied to the address
		; &H3FD8-&H3FFF (&H28 bytes will be copied)
		; the contents of registers after executing the command:
		; IX=&H1FD8, IY=&H3FD8, R5=0

--------------------

Mnemonic:	BNDM (Byte Down Multibyte)
Syntax:		BNDM register array
Execution:
	 _ _ _  Rf _ _ _             _ _ _  Rl _ _ _
	 _ _ _ _ _ _ _ _  -> ... ->  _ _ _ _ _ _ _ _  --> void
	MSB                                       LSB

Description:	Shifts the contents of a register array to the right in unit
		of bytes. The high-order byte remains unchanged.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		BNDM R67..R64		;R64 <- R65
					;R65 <- R66
					;R66 <- R67

		BNDM I27..I25

--------------------

Mnemonic:	BNUM (Byte Up Multibyte)
Syntax:		BNUM register array
Execution:
	          _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _
	         MSB                                       LSB

Description:	Shifts the contents of a register array to the left in unit of
		bytes. The low-order byte remains unchanged.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		BNUM R11..R14		;R14 <- R13
					;R13 <- R12
					;R12 <- R11

		BNUM I25..I27

--------------------

Mnemonic:	BIT (Bit Test)
Syntax:		BIT dst, src
Execution:	NOT dst AND src
Description:	Logically ANDs the source and the negated destination, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C=0, H=0, V=0, Z, LZ and UZ change
Options:
		BIT Rd,Rs	;the source and destination register must
				;belong to different register banks
		BIT Rd,Im8
Examples:
		BIT R83,R17
		BIT I10,R100
		BIT R90,I41
		BIT R10,&H05		;Zero Flag if bits 0 and 2 of the
					;register R10 are set

--------------------

Mnemonic:	BIU (Bit Up)
Syntax:		BIU Reg
Execution:
	  _       _ _ _ _ _ _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <-- "0"
	Carry    MSB           LSB

Description:	Shifts the contents of a register one bit to the left. The
		least significant bit receives a 0, while the data from the
		most significant bit moves to the Carry flag register.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction AD.
Example:
		BIU R17

--------------------

Mnemonic:	BIUM (Bit Up Multibyte)
Syntax:		BIUM register array
Execution:
	  _       _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <--  "0"
	Carry    MSB                                       LSB

Description:	Shifts the contents of a register array one bit to the left.
		The least significant bit of the low-order byte receives a 0,
		while the data from the most significant bit of the high-order
		byte moves to the Carry flag register.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction ADM.
Examples:
		BIUM R80..R87
		BIUM I24..I31

--------------------

Mnemonic:	BUP (Block Up)
Syntax:		BUP Reg
Execution:
		+->  IX <- IX + 1
		|    IY <- IY + 1
		|    (IY) <- (IX)
		|    Reg <- Reg - 1
		+--  repeat if Reg <> 0

Description:	Copies a block of memory where:
		IX-register = original block beginning address - 1
		IY-register = destination beginning address - 1
		Reg = number of transferred bytes
		The interrupts can be serviced during the transfer.
Flags:		none affected
Example:
		LD R5,&H28
		LDW IX,&H1FFF
		LDW IY,&H3FFF
		BUP R5
		; the memory block &H2000-&H2027 will be copied to the address
		; &H4000-&H4027 (&H28 bytes will be copied)
		; the contents of registers after executing the command:
		; IX=&H2027, IY=&H4027, R5=0

--------------------

Mnemonic:	BYD (Byte Down)
Syntax:		BYD Reg
Execution:
	                 _ _ _ _ _ _ _ _
	"00000000"  -->  _ _ _ _ _ _ _ _  -->  void
	                MSB           LSB

Description:	Writes 0 to a register.
Flags:		C=0, H=0, V=0, Z=1, UZ=1, LZ=1
Example:
		BYD R17

--------------------

Mnemonic:	BYDM (Byte Down Multibyte)
Syntax:		BYDM register array
Execution:
	                 _ _ _  Rf _ _ _             _ _ _  Rl _ _ _
	"00000000"  -->  _ _ _ _ _ _ _ _  -> ... ->  _ _ _ _ _ _ _ _  --> void
	                MSB                                       LSB

Description:	Shifts the contents of a register array to the right in unit
		of bytes. The high-order byte receive O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		BYDM R67..R64		;R64 <- R65
					;R65 <- R66
					;R66 <- R67
					;R67 <- 0

		BYDM I51..I50

--------------------

Mnemonic:	BYU (Byte Up)
Syntax:		BYU Reg
Execution:
	           _ _ _ _ _ _ _ _
	void  <--  _ _ _ _ _ _ _ _  <--  "00000000"
	          MSB           LSB

Description:	Writes 0 to a register.
Flags:		C=0, H=0, V=0, Z=1, UZ=1, LZ=1
Example:
		BYU R17

--------------------

Mnemonic:	BYUM (Byte Up Multibyte)
Syntax:		BYUM register array
Execution:
	          _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <--  "00000000"
	         MSB                                       LSB

Description:	Shifts the contents of a register array to the left in unit of
		bytes. The low-order byte receives O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		BYUM R11..R14		;R14 <- R13
					;R13 <- R12
					;R12 <- R11
					;R11 <- 0

		BYUM I50..I51

--------------------

Mnemonic:	CAL (Subroutine Call)
Syntax:		CAL Condition,Im16
Execution:	SP <- SP - 2
		(SP) <- PC
		PC <- Im16
Description:	Pushes the PC contents on the stack, then jumps to an address
		specified by 16-bit immediate data when the condition is met.
Flags:		none affected
Examples:
		CAL &H7D26	;unconditional call
		CAL C,&H7D26	;call on Carry (C=1)
		CAL NC,&H7D26	;call on Not Carry (C=0)
		CAL H,&H7D26	;call on Half Carry (H=1)
		CAL NH,&H7D26	;call on Not Half Carry (H=0)
		CAL V,&H7D26	;call on Overflow (V=1)
		CAL NV,&H7D26	;call on No Overflow (V=0)
		CAL Z,&H7D26	;call on Zero (Z=1)
		CAL NZ,&H7D26	;call on Not Zero (Z=0)
		CAL UZ,&H7D26	;call on Upper Zero (UZ=1)
		CAL NUZ,&H7D26	;call on Not Upper Zero (UZ=0)
		CAL LZ,&H7D26	;call on Lower Zero (LZ=1)
		CAL NLZ,&H7D26	;call on Not Lower Zero (LZ=0)
		CAL K,&H7D26	;call if key pressed (KY input <> 0)
		CAL NK,&H7D26	;call if key not pressed (KY input = 0)

--------------------

Mnemonic:	CMP (Complement)
Syntax:		CMP Reg
Execution:	reg <- 0-reg
Description:	Provides a twos complement of the operand.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction SB, for example Carry is reset if result=0,
		set if result<>0.
Example:
		CMP R17

--------------------

Mnemonic:	CMPB (Complement BCD)
Syntax:		CMPB Reg
Execution:	reg <- 0-reg (decimal)
Description:	Negates a BCD number.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction SBB.
Example:
		CMPB R17

--------------------

Mnemonic:	CMPBM (Complement BCD Multibyte)
Syntax:		CMPBM dst
Execution:	register_array <- 0 - register_array (decimal)
Description:	Negates a BCD number in a register array.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction SBBM.
Examples:
		CMPBM R17..R22
		CMPBM I42..I46

--------------------

Mnemonic:	CMPM (Complement Multibyte)
Syntax:		CMPM dst
Execution:	register_array <- 0 - register_array
Description:	Provides a twos complement of the register array.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction SBM.
Examples:
		CMPM R17..R22
		CMPM I40..I47

--------------------

Mnemonic:	DID (Digit Down)
Syntax:		DID Reg
Execution:
	             _ _ _ _ _ _ _ _
	"0000"  -->  _ _ _ _ _ _ _ _  -->  void
	            MSB           LSB

Description:	Shifts the contents of a register to the right by 4 bits. The
		high-order digit bits receive O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Example:
		DID R17

--------------------

Mnemonic:	DIDM (Digit Down Multibyte)
Syntax:		DIDM register array
Execution:
	             _ _ _  Rf _ _ _               _ _ _  Rl _ _ _
	"0000"  -->  _ _ _ _ _ _ _ _  --> ... -->  _ _ _ _ _ _ _ _  -> void
	            MSB                                         LSB

Description:	Shifts the contents of a register array to the right by
		4 bits. The high-order digit bits of the high-order byte
		receive O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		DIDM R20..R17
		DIDM I53..I50

--------------------

Mnemonic:	DIU (Digit Up)
Syntax:		DIU Reg
Execution:
	           _ _ _ _ _ _ _ _
	void  <--  _ _ _ _ _ _ _ _  <--  "0000"
	          MSB           LSB

Description:	Shifts the contents of a register to the left by 4 bits. The
		low-order digit bits receive O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Example:
		DIU R17

--------------------

Mnemonic:	DIUM (Digit Up Multibyte)
Syntax:		DIUM register array
Execution:
	          _ _ _  Rl _ _ _               _ _ _  Rf _ _ _
	void <--  _ _ _ _ _ _ _ _  <-- ... <--  _ _ _ _ _ _ _ _  <-- "0000"
	         MSB                                         LSB

Description:	Shifts the contents of a register array to the left by
		4 bits. The low-order digit bits of the low-order byte
		receive O's.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		DIUM R112..R119
		DIUM I50..I53

--------------------

Mnemonic:	GST (Get Status)
Syntax:		GST Reg,Sreg
Execution:	reg <- status_register
Description:	Reads the contents of a specified status register to a data
		register.
Flags:		none affected
Examples:
		GST R0,IE	;Interrupt Enable Register
		GST R18,DS	;Data Segment
		GST R22,PD	;8-bit port
		GST R66,KY	;Keyboard Input Port
		GST R81,F	;Flags
		GST R99,AS	;Address Select Register

--------------------

Mnemonic:	IJMP (Indirect Jump)
Syntax:		IJMP 16-bit-register
Execution:	PC <- 16-bit-register
Description:	Indirect jump to the address pointed to by a 16-bit register.
Flags:		none affected
Examples:
		IJMP IX
		IJMP IY
		IJMP IZ
		IJMP V3
		IJMP V2
		IJMP V1
		IJMP V0
		IJMP SP
		IJMP R80,R7
		IJMP R79,I15

--------------------

Mnemonic:	JMP (Absolute Jump)
Syntax:		JMP Condition,Im16
Execution:	PC <- Im16
Description:	Jumps to an address specified by 16-bit immediate data when
		the condition is met.
Flags:		none affected
Examples:
		JMP &H7D26	;unconditional jump
		JMP C,&H7D26	;jump on Carry (C=1)
		JMP NC,&H7D26	;jump on Not Carry (C=0)
		JMP H,&H7D26	;jump on Half Carry (H=1)
		JMP NH,&H7D26	;jump on Not Half Carry (H=0)
		JMP V,&H7D26	;jump on Overflow (V=1)
		JMP NV,&H7D26	;jump on No Overflow (V=0)
		JMP Z,&H7D26	;jump on Zero (Z=1)
		JMP NZ,&H7D26	;jump on Not Zero (Z=0)
		JMP UZ,&H7D26	;jump on Upper Zero (UZ=1)
		JMP NUZ,&H7D26	;jump on Not Upper Zero (UZ=0)
		JMP LZ,&H7D26	;jump on Lower Zero (LZ=1)
		JMP NLZ,&H7D26	;jump on Not Lower Zero (LZ=0)
		JMP K,&H7D26	;jump if key pressed (KY input <> 0)
		JMP NK,&H7D26	;jump if key not pressed (KY input = 0)

--------------------

Mnemonic:	LD (Load)
Syntax:		LD dst,src
Execution:	dst <- src
Description:	Transfers data to a register.
Flags:		none affected
Options:
		LD Rd,Rs		;the source and destination register
					;must belong to different banks

		LD Rd,Im8

		LD Rd,Rd,Im8		;load registers in both banks

		LD Rd,(IX)-
		LD Rd,(IY)-
		LD Rd,(IZ)-
		LD Rd,(SP)-
		
		LD Rd,(IX)+
		LD Rd,(IY)+
		LD Rd,(IZ)+
		LD Rd,(SP)+		;can be noted as POP Rd

		LD Rd,(IX+/-Im8)	;immediate offset in range 0..255
		LD Rd,(IY+/-Im8)
		LD Rd,(IZ+/-Im8)
		LD Rd,(SP+/-Im8)
Examples:
		LD R10,R70
		LD R80,R20
		LD I25,R120
		LD R121,I44
		LD R16,&H55
		LD R16,R80,&HAB
		LD R110,(IX)+		;R110 <- (IX); IX <- IX + 1
		LD R47,(IY)-		;R47 <- (IY); IY <- IY - 1
		LD R22,(IX+&H43)
		LD R99,(IZ-255)

--------------------

Mnemonic:	LDH (Load Higher Digit)
Syntax:		LDH dst,src
Execution:	lower digit of dst <- upper digit of src
Description:	Transfers the upper digit of the source register to the lower
		digit of the destination register. Both registers must belong
		to different banks.
Flags:		none affected
Examples:
		LD R10,&H34
		LD R70,&H56
		LDH R10,R70	;R10 contains &H35

		LDH R96,I9
		LDH I22,R85

--------------------

Mnemonic:	LDHM (Load Higher Digits Multibyte)
Syntax:		LDHM dst,src
Execution:	lower digits of dst <- upper digits of src
Description:	Transfers the upper digits of the source register array to the
		lower digits of the destination register array. Both arrays
		must belong to different banks.
Flags:		none affected
Examples:
		LD R10,&H34
		LD R11,&H56
		LD R74,&HAB
		LD R75,&HCD
		LDHM R10..R11,R74..R75	;R10=&H3A, R11=&H5C

		LDHM R83..R86,I51..I54
		LDHM I40..I46,R72..R78

--------------------

Mnemonic:	LDHS (Load Higher Digit then Swap Digits)
Syntax:		LDHS dst,src
Execution:	lower digit of dst <- upper digit of src, swap digits in dst
Description:	Transfers the upper digit of the source register to the lower
		digit of the destination register, then swaps digits in the
		destination register. Both registers must belong to different
		banks.
Flags:		none affected
Examples:
		LD R20,&HAB
		LD R80,&HCD
		LDHS R80,R20	;R80 contains &HAC

		LDHS I12,R93
		LDHS R86,I19

--------------------

Mnemonic:	LDHSM (Load Higher Digits then Swap Digits, Multibyte)
Syntax:		LDHSM dst,src
Execution:	lower digits of dst <- upper digits of src, swap digits in dst
Description:	Transfers the upper digits of the source register array to the
		lower digits of the destination register array, then swaps
		digits in all registers of the destination array. Both arrays
		must belong to different banks.
Flags:		none affected
Examples:
		LD R20,&HAB
		LD R21,&HCD
		LD R84,&H67
		LD R85,&H89
		LDHSM R84..R85,R20..R21	;R84=&HA6, R85=&HC8

		LDHSM I34..I36,R106..R108
		LDHSM R96..R103,I32..I39

--------------------

Mnemonic:	LDL (Load Lower Digit)
Syntax:		LDL dst,src
Execution:	upper digit of dst <- lower digit of src
Description:	Transfers the lower digit of the source register to the upper
		digit of the destination register. Both registers must belong
		to different banks.
Flags:		none affected
Examples:
		LD R10,&H34
		LD R70,&H56
		LDL R10,R70	;R10 contains &H64

		LDL I8,R97
		LDL R84,I23

--------------------

Mnemonic:	LDLM (Load Lower Digits Multibyte)
Syntax:		LDLM dst,src
Execution:	upper digits of dst <- lower digits of src
Description:	Transfers the lower digits of the source register array to the
		upper digits of the destination register array. Both arrays
		must belong to different banks.
Flags:		none affected
Examples:
		LD R30,&H34
		LD R31,&H56
		LD R78,&HAB
		LD R79,&HCD
		LDLM R78..R79,R30..R31	;R78=&H4B, R79=&H6D

		LDLM I12..I14,R100..R102
		LDLM R88..R95,I24..I31

--------------------

Mnemonic:	LDLS (Load Lower Digit then Swap Digits)
Syntax:		LDLS dst,src
Execution:	upper digit of dst <- lower digit of src, swap digits in dst
Description:	Transfers the lower digit of the source register to the upper
		digit of the destination register, then swaps digits in the
		destination register. Both registers must belong to different
		banks.
Flags:		none affected
Examples:
		LD R20,&HAB
		LD R80,&HCD
		LDLS R80,R20	;R80 contains &HDB

		LDLS R92,I13
		LDLS I18,R87

--------------------

Mnemonic:	LDLSM (Load Lower Digits then Swap Digits, Multibyte)
Syntax:		LDLSM dst,src
Execution:	upper digits of dst <- lower digits of src, swap digits in dst
Description:	Transfers the lower digits of the source register array to the
		upper digits of the destination register array, then swaps
		digits in all registers of the destination array. Both arrays
		must belong to different banks.
Flags:		none affected
Examples:
		LD R24,&HAB
		LD R25,&HCD
		LD R80,&H34
		LD R81,&H56
		LDLSM R80..R81,R24..R25	;R80=&H4B, R81=&H6D

		LDLSM R107..R110,I51..I54
		LDLSM I48..I54,R88..R94

--------------------

Mnemonic:	LDM (Load Multibyte)
Syntax:		LDM dst,src
Execution:	register array <- source
Description:	Transfers up to 8 bytes to an array of data registers.
Flags:		none affected
Options:
		LDM Rf..Rl,Im5		;load 5-bit immediate data to all
					;registers of specified array

		LDM Rf..Rl,Rf..Rl,Im5	;load register arrays in both banks

		LDM Rdf..Rdl,Rsf..Rsl	;the source and destination arrays
					;must belong to different banks

		LDM Rf..Rl,(IX)-
		LDM Rf..Rl,(IY)-
		LDM Rf..Rl,(IZ)-
		LDM Rf..Rl,(SP)-

		LDM Rf..Rl,(IX)+
		LDM Rf..Rl,(IY)+
		LDM Rf..Rl,(IZ)+
		LDM Rf..Rl,(SP)+

		LDM Rf..Rl,(IX+/-Im5)	;immediate offset in range 0..31
		LDM Rf..Rl,(IY+/-Im5)
		LDM Rf..Rl,(IZ+/-Im5)
		LDM Rf..Rl,(SP+/-Im5)
Examples:
		;immediate data to a single register array
		LDM R16..R18,&H0F		;R16 <- &H0F
						;R17 <- &H0F
						;R18 <- &H0F

		;immediate data to register arrays in both register banks
		LDM R16..R18,R80..R82,&H1A	;R16 <- &H1A
						;R17 <- &H1A
						;R18 <- &H1A
						;R80 <- &H1A
						;R81 <- &H1A
						;R82 <- &H1A

		;register array to register array
		LDM R16..R18,R48..R50		;R16 <- R48
						;R17 <- R49
						;R18 <- R50

		;register array to indirectly specified register array
		PST AS,&H54			;AS points to R42
		LDM I0..I2,R80..R82		;R42 <- R80
						;R43 <- R81
						;R44 <- R82

		;indirectly specified register array to register array
		PST AS,&H05
		; address of the starting source register = 32+2
		LDM R109..R111,I37..I39		;R109 <- R34
						;R110 <- R35
						;R111 <- R36

		LDM R16..R18,(IX)+		;R16 <- (IX); IX <- IX + 1
						;R17 <- (IX); IX <- IX + 1
						;R18 <- (IX); IX <- IX + 1

		LDM R84..R81,(IY)-		;R84 <- (IY); IY <- IY - 1
						;R83 <- (IY); IY <- IY - 1
						;R82 <- (IY); IY <- IY - 1
						;R81 <- (IY); IY <- IY - 1

		;indexed address mode, positive offset
		LDM R21..R23,(IX+4)		;R21 <- (IX+4)
						;R22 <- (IX+5)
						;R23 <- (IX+6)

		;indexed address mode, negative offset
		LDM R78..R76,(IZ-7)		;R78 <- (IZ-7)
						;R77 <- (IZ-8)
						;R76 <- (IZ-9)

--------------------

Mnemonic:	LDS (Load Then Swap Digits)
Syntax:		LDS dst,src
Execution:	dst <- src, swap digits in dst
Description:	Transfers the source register to the destination register,
		then swaps digits in the destination register. Both registers
		must belong to different banks.
Flags:		none affected
Examples:
		LDS R10,R70
		LDS R80,R20
		LDS I1,R100
		LDS R100,I1

--------------------

Mnemonic:	LDSM (Load Then Swap Digits Multibyte)
Syntax:		LDSM dst,src
Execution:	dst <- src, swap digits in each byte of dst
Description:	Transfers the source array to the destination array, then
		swaps digits in all bytes of the destination array. Both
		arrays must belong to different register banks.
Flags:		none affected
Examples:
		LDSM R2..R4,R74..R76
		LDSM R80..R83,R32..R35
		LDSM I9..I13,R113..R117
		LDSM R99..R101,I51..I53

--------------------

Mnemonic:	LDW (Load Word)
Syntax:		LDW dst,src
Execution:	dst <- src
Description:	Transfers immediate data to a 16-bit register.
Flags:		none affected
Options:
		LDW IX,Im16
		LDW IY,Im16
		LDW IZ,Im16
		LDW V3,Im16
		LDW V2,Im16
		LDW V1,Im16
		LDW V0,Im16
		LDW SP,Im16
Examples:
		LDW IX,&H1234
		LDW SP,&HFFFF

--------------------

Mnemonic:	MTB (Multiply by Two BCD)
Syntax:		MTB Reg
Execution:	Reg <- Reg * 2 , produces decimal result
Description:	Multiplies the contents of the register by two. The register
		is assumed to contain two digits in binary-coded decimal (BCD)
		form.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction ADB.
Example:
		MTB R89

--------------------

Mnemonic:	MTBM (Multiply by Two BCD Multibyte)
Syntax:		MTBM register array
Execution:	register_array <- register_array * 2 , produces decimal result
Description:	Multiplies the contents of the register array by two. Each
		byte is assumed to contain two digits in binary-coded decimal
		(BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction ADBM.
Examples:
		MTBM R19..R23
		MTBM I10..I14

--------------------

Mnemonic:	NA (Logical NAND)
Syntax:		NA dst,src
Execution:	dst <- NOT (dst AND src)
Description:	Logically NANDs the source and the destination and stores the
		result in the destination.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Options:
		NA Rd,Rs	;the source and destination register must
				;belong to different register banks
		NA Rd,Im8
		NA (IX),Rs
		NA (IY),Rs
		NA (IX),Im8
		NA (IY),Im8
Examples:
		NA R10,R70
		NA R80,R20
		NA I10,R70
		NA R80,I20
		NA R16,&H55
		NA (IX),R110
		NA (IY),R47
		NA (IX),&HFE
		NA (IY),&H6A

--------------------

Mnemonic:	NAM (Logical NAND Multibyte)
Syntax:		NAM dst,src
Execution:	dst <- NOT (dst AND src)
Description:	Logically NANDs the source and the destination array and
		stores the result in the destination array. Both arrays must
		belong to different register banks.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Examples:
		NAM R10..R12,R74..R76
		NAM I33..I34,R97..R98
		NAM R105..R110,I9..I14

--------------------

Mnemonic:	NOP (No Operation)
Syntax:		NOP
Description:	Increments the program counter.
Flags:		none affected
Examples:
		NOP

--------------------

Mnemonic:	OFF (Power Off)
Syntax:		OFF
Description:	Puts the microprocessor into sleep mode. Following registers
		are changed:
		- KY <- &H40 (active KAC output driving the [AC] key)
		The processor can be waken up (i.e. restarted from the address
		&H0000) by following events:
		- pressing the [AC] key, i.e. voltage level change on the KI0
		  input from high to low
		- turning the power switch off then on, i.e. voltage level
		  change on the SW input from high to low
Example:
		OFF

-------------------

Mnemonic:	OR (Logical OR)
Syntax:		OR dst,src
Execution:	dst <- dst OR src
Description:	Logically ORs the source and the destination and stores the
		result in the destination.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Options:
		OR Rd,Rs	;the source and destination register must
				;belong to different register banks
		OR Rd,Im8
		OR (IX),Rs
		OR (IY),Rs
		OR (IX),Im8
		OR (IY),Im8
Examples:
		OR R10,R70
		OR R80,R20
		OR I25,R64
		OR R71,I44
		OR R16,&H55
		OR (IX),R110
		OR (IY),R47
		OR (IX),&HFE
		OR (IY),&H6A

--------------------

Mnemonic:	ORM (Logical OR Multibyte)
Syntax:		ORM dst,src
Execution:	dst <- dst OR src
Description:	Logically ORs two register arrays and stores the result in
		the destination array. Both arrays must belong to different
		register banks.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Examples:
		ORM R41..R44,R97..R100
		ORM I0..I7,R72..R79
		ORM R98..R98,I58..I58

--------------------

Mnemonic:	PLA (Put LCD Address)
Syntax:		PLA 16-bit-register
Execution:	display memory address register LA <- 16-bit-register
Description:	Specifies the display memory address with the contents of a
		16-bit register.
Flags:		none affected
Example:
		LDW	IY,&H02FF
		PLA	IY	;display memory starts at the address &H0300

--------------------

Mnemonic:	PST (Put Status)
Syntax:		PST Sreg,src
Execution:	status_register <- src
Description:	Writes data to a specified status register.
Flags:		none affected except when writting to the F register
Options:
		PST Sreg,Rs
		PST Sreg,Im7/Im8
Examples:
		; 8-bit immediate or register operand
		PST IE,R0	;Interrupt Enable Register
		PST IE,&H8F	;enable all interrupts

		PST DS,R18	;Data Segment
		PST DS,&HF3

		PST PD,R22	;8-bit port
		PST PD,&HAB

		PST KY,R66	;Keyboard Output Port
		PST KY,&H48	;select the key output KO5

		; 7-bit immediate or register operand
		PST AS,R99	;Address Select Register
		PST AS,&H02	;point to R1

		; 8-bit register operand
		PST F,R81	;Flags

		; 7-bit immediate operand
		PST PE,&H04	;4-bit output port
		PST S4,&H00	;unknown status register temporarily named S4
		PST S5,&H2F	;display clock divisor
		PST S6,&H77	;display height and control
		PST S7,&H17	;display width
		PST S8,&H40	;unknown status register temporarily named S8
		PST TM,&H0E	;timer divisor

--------------------

Mnemonic:	ROD (Rotate Down)
Syntax:		ROD Reg
Execution:

	+ - - - - - - - - - - - - - - - +
	|   _       _ _ _ _ _ _ _ _     |
	+ - _  -->  _ _ _ _ _ _ _ _  -> +
	  Carry    MSB           LSB

Description:	Circulary shifts the register contents one bit to the right.
Flags:		C changes, H=0, V=0, Z, UZ and LZ change
Example:
		ROD R17

--------------------

Mnemonic:	RODM (Rotate Down Multibyte)
Syntax:		RODM Reg
Execution:

	+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
	|   _       _ _ _  Rf _ _ _             _ _ _  Rl _ _ _     |
	+ - _  -->  _ _ _ _ _ _ _ _  -> ... ->  _ _ _ _ _ _ _ _  -> +
	  Carry    MSB                                       LSB

Description:	Circulary shifts a register array one bit to the right.
Flags:		C changes, H=0, V=0, Z, UZ and LZ change
Examples:
		RODM R20..R17
		RODM I47..I40

--------------------

Mnemonic:	ROU (Rotate Up)
Syntax:		ROU Reg
Execution:

	+ - - - - - - - - - - - - - - - +
	|   _       _ _ _ _ _ _ _ _     |
	+ - _  <--  _ _ _ _ _ _ _ _  <- +
	  Carry    MSB           LSB

Description:	Circulary shifts the register contents one bit to the left.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent reg+reg+carry operation.
Example:
		ROU R17

--------------------

Mnemonic:	ROUM (Rotate Up Multibyte)
Syntax:		ROUM Reg
Execution:

	+ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +
	|   _       _ _ _  Rl _ _ _             _ _ _  Rf _ _ _     |
	+ - _  <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <- +
	  Carry    MSB                                       LSB

Description:	Circulary shifts an array of registers one bit to the left.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent array+array+carry operation.
Examples:
		ROUM R17..R20
		ROUM I25..I28

--------------------

Mnemonic:	RTN (Return From Subroutine)
Syntax:		RTN Condition
Execution:	PC <- (SP)
		SP <- SP + 2
Description:	Returns when the condition is met.
Flags:		none affected
Examples:
		RTN		;unconditional return
		RTN C		;return on Carry (C=1)
		RTN NC		;return on Not Carry (C=0)
		RTN H		;return on Half Carry (H=1)
		RTN NH		;return on Not Half Carry (H=0)
		RTN V		;return on Overflow (V=1)
		RTN NV		;return on No Overflow (V=0)
		RTN Z		;return on Zero (Z=1)
		RTN NZ		;return on Not Zero (Z=0)
		RTN UZ		;return on Upper Zero (UZ=1)
		RTN NUZ		;return on Not Upper Zero (UZ=0)
		RTN LZ		;return on Lower Zero (LZ=1)
		RTN NLZ		;return on Not Lower Zero (LZ=0)
		RTN K		;return if key pressed (KY input <> 0)
		RTN NK		;return if key not pressed (KY input = 0)

--------------------

Mnemonic:	SB (Subtract)
Syntax:		SB dst,src
Execution:	dst <- dst - src
Description:	Subtracts the source from the destination and stores the
		result in the destination.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SB Rd,Rs	;the source and destination register must
				;belong to different register banks
		SB Rd,Im8
		SB (IX),Rs
		SB (IY),Rs
		SB (IX),Im8
		SB (IY),Im8
Examples:
		SB R10,R70
		SB R80,R20
		SB I25,R112
		SB R67,I44
		SB R16,&H55
		SB (IX),R110
		SB (IY),R47
		SB (IX),&HFE
		SB (IY),&H6A

--------------------

Mnemonic:	SBB (Subtract BCD)
Syntax:		SBB dst,src
Execution:	dst <- dst - src, produces a decimal result
Description:	Subtracts the source from the destination, and stores the
		result in the destination. Each byte is assumed to contain
		two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBB Rd,Rs	;the source and destination register must
				;belong to different register banks
		SBB Rd,Im8
		SBB (IX),Rs
		SBB (IY),Rs
		SBB (IX),Im8
		SBB (IY),Im8
Examples:
		SBB R10,R70
		SBB R80,R20
		SBB I25,R88
		SBB R92,I44
		SBB R16,&H55
		SBB (IX),R110
		SBB (IY),R47
		SBB (IX),&HFE
		SBB (IY),&H6A

--------------------

Mnemonic:	SBBC (Subtract BCD With Carry)
Syntax:		SBBC dst,src
Execution:	dst <- dst - src - Carry, produces decimal result
Description:	Subtracts the source and the carry bit from the destination
		and stores the result in the destination. Each byte is assumed
		to contain two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		SBBC Rd,Im8
Examples:
		SBBC R10,R70
		SBBC R80,R20
		SBBC I25,R88
		SBBC R92,I44
		SBBC R16,&H55

--------------------

Mnemonic:	SBBCM (Subtract BCD With Carry Multibyte)
Syntax:		SBBCM dst,src
Execution:	dst <- dst - src - Carry, produces decimal result
Description:	Subtracts the source and the carry bit from the destination
		array and stores the result in the destination array. Each
		byte is assumed to contain two digits in binary-coded decimal
		(BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBBCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		SBBCM R10..R12,R66..R68
		SBBCM I24..I31,R96..R111
		SBBCM R99..R101,I43..I45
		SBBCM R96..R101,&H18

--------------------

Mnemonic:	SBBM (Subtract BCD Multibyte)
Syntax:		SBBM dst,src
Execution:	dst <- dst - src, produces a decimal result
Description:	Subtracts the source from the destination array, and stores
		the result in the destination array. Each byte is assumed to
		contain two digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		SBBM R8..R15,R72..R79
		SBBM I24..I31,R96..R111
		SBBM R99..R101,I43..I45
		SBBM R75..R78,&H07

--------------------

Mnemonic:	SBC (Subtract With Carry)
Syntax:		SBC dst,src
Execution:	dst <- dst - src - Carry
Description:	Subtracts the source and the carry bit from the destination
		and stores the result in the destination.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		SBC Rd,Im8
Examples:
		SBC R10,R70
		SBC R80,R20
		SBC I25,R88
		SBC R92,I44
		SBC R16,&H55

--------------------

Mnemonic:	SBCM (Subtract With Carry Multibyte)
Syntax:		SBCM dst,src
Execution:	dst <- dst - src - Carry
Description:	Subtracts the source and the carry bit from the destination
		array, and stores the result in the destination array.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		SBCM R80..R87,R24..R31
		SBCM I24..I31,R96..R111
		SBCM R99..R101,I43..I45
		SBCM R1..R5,&H1A

--------------------

Mnemonic:	SBM (Subtract Multibyte)
Syntax:		SBM dst,src
Execution:	dst <- dst - src
Description:	Subtracts the source from the destination array and stores
		the result in the destination array.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		SBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		SBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		SBM R10..R11,R74..R75
		SBM I24..I31,R88..R95
		SBM R99..R101,I43..I45
		SBM R88..R95,&H0B

--------------------

Mnemonic:	SBW (Subtract Word)
Syntax:		SBW dst,src
Execution:	dst <- dst - src
Description:	Subtracts the source from the destination and stores the
		result in the destination.
Flags:		none affected
Options:
		SBW IX,Im7
		SBW IY,Im7
		SBW IZ,Im7
		SBW SP,Im7

		SBW IX,Rs	;8-bit contents of a single data register
		SBW IY,Rs
		SBW IZ,Rs
		SBW SP,Rs
Examples:
		SBW IY,&H69		;IY <- IY - &H69
		SBW IZ,R85		;IZ <- IZ - R85

--------------------

Mnemonic:	SCAL (Short Subroutine Call)
Syntax:		SCAL Condition,Im8
Execution:	SP <- SP - 2
		(SP) <- PC
		low order byte of the PC <- Im8
Description:	Pushes the PC contents on the stack, then jumps to the
		specified address within the current memory page (256 bytes)
		when the condition is met.
Flags:		none affected
Examples:
		SCAL &H7D26	;unconditional call
		SCAL C,&H7D26	;call on Carry (C=1)
		SCAL NC,&H7D26	;call on Not Carry (C=0)
		SCAL H,&H7D26	;call on Half Carry (H=1)
		SCAL NH,&H7D26	;call on Not Half Carry (H=0)
		SCAL V,&H7D26	;call on Overflow (V=1)
		SCAL NV,&H7D26	;call on No Overflow (V=0)
		SCAL Z,&H7D26	;call on Zero (Z=1)
		SCAL NZ,&H7D26	;call on Not Zero (Z=0)
		SCAL UZ,&H7D26	;call on Upper Zero (UZ=1)
		SCAL NUZ,&H7D26	;call on Not Upper Zero (UZ=0)
		SCAL LZ,&H7D26	;call on Lower Zero (LZ=1)
		SCAL NLZ,&H7D26	;call on Not Lower Zero (LZ=0)
		SCAL K,&H7D26	;call if key pressed (KY input <> 0)
		SCAL NK,&H7D26	;call if key not pressed (KY input = 0)

--------------------

Mnemonic:	SDN (Search Down)
Syntax:		SDN RegC, RegD
Execution:
		+->  IX <- IX - 1
		|    RegC <- RegC - 1
		+--  repeat if RegC <> 0 and RegD <> (IX)

Description:	Searches the memory for specified data.
		IX-register = beginning address + 1
		RegC (must belong to the second bank) = counter of bytes
		RegD (must belong to the first bank, indirect specification
		allowed) = searched data
		The interrupts can be serviced during the search.
Flags:		none affected
Examples:
		LD R5,&H45	;searched data
		LD R66,&H80	;maximal number of searched memory locations
		LDW IX,&H2000	;beginning address + 1
		SDN R66,R5
		; the contents of registers after executing the command:
		; IX=&H1F80, R66=0 if data not found
		; IX=&H1FD5, R66=&H55 if data found at location &H1FD5

		SDN R66,I5	;indirectly specified data register

--------------------

Mnemonic:	SJMP (Short Jump)
Syntax:		SJMP Condition,Im8
Execution:	low order byte of the PC <- Im8
Description:	Jumps to the specified address within the current memory page
		(256 bytes) when the condition is met.
Flags:		none affected
Examples:
		SJMP &H7D26	;unconditional jump
		SJMP C,&H7D26	;jump on Carry (C=1)
		SJMP NC,&H7D26	;jump on Not Carry (C=0)
		SJMP H,&H7D26	;jump on Half Carry (H=1)
		SJMP NH,&H7D26	;jump on Not Half Carry (H=0)
		SJMP V,&H7D26	;jump on Overflow (V=1)
		SJMP NV,&H7D26	;jump on No Overflow (V=0)
		SJMP Z,&H7D26	;jump on Zero (Z=1)
		SJMP NZ,&H7D26	;jump on Not Zero (Z=0)
		SJMP UZ,&H7D26	;jump on Upper Zero (UZ=1)
		SJMP NUZ,&H7D26	;jump on Not Upper Zero (UZ=0)
		SJMP LZ,&H7D26	;jump on Lower Zero (LZ=1)
		SJMP NLZ,&H7D26	;jump on Not Lower Zero (LZ=0)
		SJMP K,&H7D26	;jump if key pressed (KY input <> 0)
		SJMP NK,&H7D26	;jump if key not pressed (KY input = 0)

--------------------

Mnemonic:	ST (Store)
Syntax:		ST dst,src
Execution:	dst <- src
Description:	Transfers data to a memory location.
Flags:		none affected
Options:
		ST -(IX),Rs
		ST -(IY),Rs
		ST -(IZ),Rs
		ST -(SP),Rs		;can be noted as PUSH Rs

		ST +(IX),Rs
		ST +(IY),Rs
		ST +(IZ),Rs
		ST +(SP),Rs

		ST (IX+/-Im8),Rs	;immediate offset in range 1..256
		ST (IY+/-Im8),Rs
		ST (IZ+/-Im8),Rs
		ST (SP+/-Im8),Rs
Examples:
		ST +(IX),R110		;IX <- IX + 1; (IX) <- R110
		ST -(IY),R47		;IY <- IY - 1; (IY) <- R47
		ST (IY+10),R25
		ST (SP-&H12),R68

--------------------

Mnemonic:	STLM (Store LCD data Multibyte)
Syntax:		STLM dst,src
Execution:	memory, display driver <- register array
Description:	Transfers an array of up to 8 data registers simultaneously
		to the memory and to the display driver.
Flags:		none affected
Options:
		STLM -(IX),Rf..Rl
		STLM -(IY),Rf..Rl
		STLM -(IZ),Rf..Rl
		STLM -(SP),Rf..Rl

		STLM +(IX),Rf..Rl
		STLM +(IY),Rf..Rl
		STLM +(IZ),Rf..Rl
		STLM +(SP),Rf..Rl

Example from an FX-7500G calculator (LCD driver configuration):

		LDW	IY,&H3333		;configuration data
		STLM	-(SP),R121..R121	;first LCD driver chip
		STLM	-(SP),R57..R57		;second LCD driver chip
		ADW	SP,&H02

--------------------

Mnemonic:	STM (Store Multibyte)
Syntax:		STM dst,src
Execution:	memory block <- register array
Description:	Transfers an array of up to 8 data registers to memory.
Flags:		none affected
Options:
		STM -(IX),Rf..Rl
		STM -(IY),Rf..Rl
		STM -(IZ),Rf..Rl
		STM -(SP),Rf..Rl

		STM +(IX),Rf..Rl
		STM +(IY),Rf..Rl
		STM +(IZ),Rf..Rl
		STM +(SP),Rf..Rl

		STM (IX+/-Im5),Rf..Rl	;immediate offset in range 1..32
		STM (IY+/-Im5),Rf..Rl
		STM (IZ+/-Im5),Rf..Rl
		STM (SP+/-Im5),Rf..Rl
Examples:
		STM +(IX),R18..R16	;IX <- IX + 1; (IX) <- R18
					;IX <- IX + 1; (IX) <- R17
					;IX <- IX + 1; (IX) <- R16

		STM -(IY),R84..R81	;IY <- IY - 1; (IY) <- R84
					;IY <- IY - 1; (IY) <- R83
					;IY <- IY - 1; (IY) <- R82
					;IY <- IY - 1; (IY) <- R81

		;indexed address mode, positive offset
		STM (IX+4),R21..R23	;(IX+4) <- R21
					;(IX+5) <- R22
					;(IX+6) <- R23

		;indexed address mode, negative offset
		STM (IZ-7),R78..R76	;(IZ-7) <- R78
					;(IZ-8) <- R77
					;(IZ-9) <- R76

--------------------

Mnemonic:	SUP (Search Up)
Syntax:		SUP RegC, RegD
Execution:
		+->  IX <- IX + 1
		|    RegC <- RegC - 1
		+--  repeat if RegC <> 0 and RegD <> (IX)

Description:	Searches the memory for specified data.
		IX-register = beginning address - 1
		RegC (must belong to the second bank) = counter of bytes
		RegD (must belong to the first bank, indirect specification
		allowed) = searched data
		The interrupts can be serviced during the search.
Flags:		none affected
Examples:
		LD R5,&H45	;searched data
		LD R66,&H80	;maximal number of searched memory locations
		LDW IX,&H2000	;beginning address - 1
		SUP R66,R5
		; the contents of registers after executing the command:
		; IX=&H2080, R66=0 if data not found
		; IX=&H202B, R66=&H55 if data found at location &H202B

		SUP R66,I5	;indirectly specified data register

--------------------

Mnemonic:	SWP (Swap Digits)
Syntax:		SWP reg
		SWP reg1, reg2
Execution:	swap digits
Description:	Swaps digits in specified register(s).
Flags:		none affected
Options:
		SWP Rd		;swap digits in a single register
		SWP Rd,Rs	;swap digits in two registers which must
				;belong to different banks
Examples:
		SWP R15
		SWP R99
		SWP R10,R70
		SWP R80,R20

--------------------

Mnemonic:	SWPM (Swap Digits Multibyte)
Syntax:		SWPM register_array
		SWPM register_array1, register_array2
Execution:	swap digits
Description:	Swaps digits in all registers of specified register array(s).
Flags:		none affected
Options:
		SWPM Rf..Rl		;single register array
		SWPM Rf1..Rl1,Rf2..Rl2	;two register arrays which must
					;belong to different banks
Examples:
		SWPM R10..R15
		SWPM R99..R101
		SWPM R10..R15,R72..R77
		SWPM R82..R85,R26..R29

--------------------

Mnemonic:	TAD (Test Add)
Syntax:		TAD dst,src
Execution:	dst + src
Description:	Adds the source to the destination, but the result is not
		written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TAD Rd,Rs	;the source and destination register must
				;belong to different register banks
		TAD Rd,Im8
		TAD (IX),Rs
		TAD (IY),Rs
Examples:
		TAD R10,R70
		TAD R80,R20
		TAD I25,R88
		TAD R99,I44
		TAD R16,&H55
		TAD (IX),R110
		TAD (IY),R47

--------------------

Mnemonic:	TADB (Test Add BCD)
Syntax:		TADB dst,src
Execution:	dst + src, decimal numbers
Description:	Adds the source to the destination, but the result is not
		written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TADB Rd,Im8
		TADB (IX),Rs
		TADB (IY),Rs
Examples:
		TADB R10,R70
		TADB R80,R20
		TADB I25,R88
		TADB R99,I44
		TADB R16,&H55
		TADB (IX),R110
		TADB (IY),R47

--------------------

Mnemonic:	TADBC (Test Add BCD With Carry)
Syntax:		TADBC dst,src
Execution:	dst + src + Carry, decimal numbers
Description:	Adds the source, the destination and the carry bit, but the
		result is not written anywhere. Only the status of the flags
		is changed. Each byte is assumed to contain two digits in
		binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		TADBC Rd,Im8
Examples:
		TADBC R10,R70
		TADBC R80,R20
		TADBC I25,R88
		TADBC R99,I44
		TADBC R16,&H55

--------------------

Mnemonic:	TADBCM (Test Add BCD With Carry Multibyte)
Syntax:		TADBCM dst,src
Execution:	dst + src + Carry, decimal numbers
Description:	Adds the source and the carry bit to the destination array,
		but the result is not written anywhere. Only the status of the
		flags is changed. Each byte is assumed to contain two digits
		in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADBCM Rdf..Rdl,Rsf..Rsl;the source and destination array must
					;belong to different register banks
		TADBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TADBCM R1..R3,R65..R67
		TADBCM I24..I31,R96..R103
		TADBCM R66..R67,I58..I59
		TADBCM R10..R13,&H15

--------------------

Mnemonic:	TADBM (Add BCD Multibyte)
Syntax:		TADBM dst,src
Execution:	dst + src, decimal numbers
Description:	Adds the source to the destination array, but the result is
		not written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TADBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TADBM R0..R3,R64..R67
		ADBM I24..I31,R96..R103
		ADBM R66..R67,I58..I59
		TADBM R64..R66,&H04

--------------------

Mnemonic:	TADC (Test Add With Carry)
Syntax:		TADC dst,src
Execution:	dst + src + Carry
Description:	Adds the source, the destination and the carry bit, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADC Rd,Rs	;the source and destination register must
				;belong to different register banks
		TADC Rd,Im8
Examples:
		TADC R10,R70
		TADC R80,R20
		TADC I25,R88
		TADC R99,I44
		TADC R16,&H55

--------------------

Mnemonic:	TADCM (Test Add With Carry Multibyte)
Syntax:		TADCM dst,src
Execution:	dst + src + Carry
Description:	Adds the source and the carry bit to the destination array,
		but the result is not written anywhere. Only the status of the
		flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TADCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TADCM R80..R86,R16..R22
		TADCM I24..I31,R96..R103
		TADCM R66..R67,I58..I59
		TADCM R24..R31,&H1F

--------------------

Mnemonic:	TADM (Test Add Multibyte)
Syntax:		TADM dst,src
Execution:	dst + src
Description:	Adds the sorce to the destination array, but the result is not
		written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TADM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TADM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TADM R100..R103,R44..R47
		TADM I24..I31,R96..R103
		TADM R76..R79,I44..I47
		TADM R11..R14,&H0A

--------------------

Mnemonic:	TAN (Test Logical AND)
Syntax:		TAN dst,src
Execution:	dst AND src
Description:	Logically ANDs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Options:
		TAN Rd,Rs	;the source and destination register must
				;belong to different register banks
		TAN Rd,Im8
		TAN (IX),Rs
		TAN (IY),Rs
Examples:
		TAN R10,R70
		TAN R80,R20
		TAN I25,R101
		TAN R99,I44
		TAN R16,&H55
		TAN (IX),R110
		TAN (IY),R47

--------------------

Mnemonic:	TANM (Test Logical AND Multibyte)
Syntax:		TANM dst,src
Execution:	dst AND src
Description:	Logically ANDs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both register arrays must belong to different register banks.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		TANM R0..R7,R64..R71
		TANM R83..R87,R51..R55
		TANM I33..I34,R81..R82
		TANM R109..R111,I45..I47

--------------------

Mnemonic:	TBIU (Test Bit Up)
Syntax:		TBIU Reg
Execution:
	  _       _ _ _ _ _ _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <-- "0"
	Carry    MSB           LSB

Description:	Shifts the contents of a register one bit to the left, but the
		result is not stored. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction TAD.
Example:
		TBIU R17

--------------------

Mnemonic:	TBIUM (Bit Up Multibyte)
Syntax:		TBIUM register array
Execution:
	  _       _ _ _  Rl _ _ _             _ _ _  Rf _ _ _
	  _  <--  _ _ _ _ _ _ _ _  <- ... <-  _ _ _ _ _ _ _ _  <--  "0"
	Carry    MSB                                       LSB

Description:	Shifts the contents of a register array one bit to the left,
		but the result is not stored. Only the status of the flags is
		changed.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction TADM.
Example:
		TBIUM R80..R87

--------------------

Mnemonic:	TCMP (Complement)
Syntax:		TCMP Reg
Execution:	reg <- 0-reg
Description:	Provides a twos complement of the operand, but the result is
		not written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction TSB, for example Carry is reset if result=0,
		set if result<>0.
Example:
		TCMP R17

--------------------

Mnemonic:	TCMPB (Complement BCD)
Syntax:		TCMPB Reg
Execution:	reg <- 0-reg (decimal)
Description:	Negates a BCD number, but the result is not written anywhere.
		Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-reg operation performed by
		the instruction TSBB.
Example:
		TCMPB R17

--------------------

Mnemonic:	TCMPBM (Test Complement BCD Multibyte)
Syntax:		TCMPBM dst
Execution:	0 - register_array (decimal)
Description:	Negates a BCD number in a register array, but the result is
		not written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction TSBBM.
Example:
		TCMPBM R17..R22

--------------------

Mnemonic:	TCMPM (Test Complement Multibyte)
Syntax:		TCMPM dst
Execution:	0 - register_array
Description:	Provides a twos complement of the register array, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent 0-array operation performed by
		the instruction TSBM.
Example:
		TCMPM R17..R22

--------------------

Mnemonic:	TMTB (Test Multiply by Two BCD)
Syntax:		TMTB Reg
Execution:	Reg * 2 , produces decimal result
Description:	Multiplies the contents of the register by two, but the result
		is not written anywhere. Only the status of the flags is
		changed. The register is assumed to contain two digits in
		binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent reg+reg operation performed by
		the instruction TADB.
Example:
		TMTB R89

--------------------

Mnemonic:	TMTBM (Test Multiply by Two BCD Multibyte)
Syntax:		TMTBM register array
Execution:	register_array * 2 , produces decimal result
Description:	Multiplies the contents of a register array by two, but the
		result is not written anywhere. Only the status of the flags
		is changed. Each byte is assumed to contain two digits in
		binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
		Flags are set as by equivalent array+array operation performed
		by the instruction TADBM.
Examples:
		TMTBM R73..R76
		TMTBM I10..I14

--------------------

Mnemonic:	TNA (Test Logical NAND)
Syntax:		TNA dst,src
Execution:	NOT (dst AND src)
Description:	Logically NANDs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Options:
		TNA Rd,Rs	;the source and destination register must
				;belong to different register banks
		TNA Rd,Im8
		TNA (IX),Rs
		TNA (IY),Rs
Examples:
		TNA R10,R70
		TNA R80,R20
		TNA I10,R70
		TNA R80,I20
		TNA R16,&H55
		TNA (IX),R110
		TNA (IY),R47

--------------------

Mnemonic:	TNAM (Test Logical NAND Multibyte)
Syntax:		TNAM dst,src
Execution:	NOT (dst AND src)
Description:	Logically NANDs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Examples:
		TNAM R10..R12,R74..R76
		TNAM I33..I34,R97..R98
		TNAM R105..R110,I9..I14

--------------------

Mnemonic:	TOR (Test Logical OR)
Syntax:		TOR dst,src
Execution:	dst OR src
Description:	Logically ORs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Options:
		TOR Rd,Rs	;the source and destination register must
				;belong to different register banks
		TOR Rd,Im8
		TOR (IX),Rs
		TOR (IY),Rs
Examples:
		TOR R10,R70
		TOR R80,R20
		TOR I25,R64
		TOR R71,I44
		TOR R16,&H55
		TOR (IX),R110
		TOR (IY),R47

--------------------

Mnemonic:	TORM (Test Logical OR Multibyte)
Syntax:		TORM dst,src
Execution:	dst OR src
Description:	Logically ORs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=1, H=1, V=1, Z, UZ and LZ change
Examples:
		TORM R41..R44,R97..R100
		TORM I0..I7,R72..R79
		TORM R98..R98,I58..I58

--------------------

Mnemonic:	TRP (Trap)
Syntax:		TRP
Execution:	SP <- SP - 2
		(SP) <- PC
		PC <- R119,R55
Description:	Pushes the address of the TRP instruction on the stack, then
		jumps to an address contained in the register pair R119,R55.
Flags:		none affected
Examples:
		TRP

--------------------

Mnemonic:	TSB (Test Subtract)
Syntax:		TSB dst,src
Execution:	dst - src
Description:	Subtracts the source from the destination, but the result is
		not written anywhere. Only the status of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSB Rd,Im8
		TSB (IX),Rs
		TSB (IY),Rs
Examples:
		TSB R10,R70
		TSB R80,R20
		TSB I25,R112
		TSB R67,I44
		TSB R16,&H55
		TSB (IX),R110
		TSB (IY),R47

--------------------

Mnemonic:	TSBB (Test Subtract BCD)
Syntax:		TSBB dst,src
Execution:	dst - src, decimal numbers
Description:	Subtracts the source from the destination, but the result is
		not written anywhere. Only the status of the flags is changed.
		Each byte is assumed to contain two digits in binary-coded
		decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSBB Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSBB Rd,Im8
		TSBB (IX),Rs
		TSBB (IY),Rs
Examples:
		TSBB R10,R70
		TSBB R80,R20
		TSBB I25,R88
		TSBB R92,I44
		TSBB R16,&H55
		TSBB (IX),R110
		TSBB (IY),R47

--------------------

Mnemonic:	TSBBC (Test Subtract BCD With Carry)
Syntax:		TSBBC dst,src
Execution:	dst - src - Carry, decimal numbers
Description:	Subtracts the source and the carry bit from the destination,
		but the result is not written anywhere. Only the status of the
		flags is changed. Each byte is assumed to contain two digits
		in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSBBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSBBC Rd,Im8
Examples:
		TSBBC R10,R70
		TSBBC R80,R20
		TSBBC I25,R88
		TSBBC R92,I44
		TSBBC R16,&H55

--------------------

Mnemonic:	TSBBCM (Test Subtract BCD With Carry Multibyte)
Syntax:		TSBBCM dst,src
Execution:	dst - src - Carry, decimal numbers
Description:	Subtracts the sourceand the carry bit from the destination
		array, but the result is not written anywhere. Only the status
		of the flags is changed. Each byte is assumed to contain two
		digits in binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSBBCM Rdf..Rdl,Rsf..Rsl;the source and destination array must
					;belong to different register banks
		TSBBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TSBBCM R10..R12,R66..R68
		TSBBCM I24..I31,R96..R111
		TSBBCM R99..R101,I43..I45
		TSBBCM R96..R100,&H12

--------------------

Mnemonic:	TSBBM (Test Subtract BCD Multibyte)
Syntax:		TSBBM dst,src
Execution:	dst - src, decimal numbers
Description:	Subtracts the source from the destination array, but the
		result is not written anywhere. Only the status of the flags
		is changed. Each byte is assumed to contain two digits in
		binary-coded decimal (BCD) form.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSBBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TSBBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TSBBM R8..R15,R72..R79
		TSBBM I24..I31,R96..R111
		TSBBM R99..R101,I43..I45
		TSBBM R72..R79,&H06

--------------------

Mnemonic:	TSBC (Test Subtract With Carry)
Syntax:		TSBC dst,src
Execution:	dst - src - Carry
Description:	Subtracts the source and the carry bit from the destination,
		but the result is not written anywhere. Only the status of the
		flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
Options:
		TSBC Rd,Rs	;the source and destination register must
				;belong to different register banks
		TSBC Rd,Im8
Examples:
		TSBC R10,R70
		TSBC R80,R20
		TSBC I25,R88
		TSBC R92,I44
		TSBC R16,&H55

--------------------

Mnemonic:	TSBCM (Test Subtract With Carry Multibyte)
Syntax:		TSBCM dst,src
Execution:	dst - src - Carry
Description:	Subtracts the source and the carry bit from the destination
		array, but the result is not written anywhere. Only the status
		of the flags is changed.
Flags:		C, H, V, Z, UZ and LZ change
		TSBCM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TSBCM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TSBCM R80..R87,R24..R31
		TSBCM I24..I31,R96..R111
		TSBCM R99..R101,I43..I45
		TSBCM R8..R12,&H1A

--------------------

Mnemonic:	TSBM (Test Subtract Multibyte)
Syntax:		TSBM dst,src
Execution:	dst - src
Description:	Subtracts the source from the destination array, but the
		result is not written anywhere. Only the status of the flags
		is changed.
Flags:		C, H, V, Z, UZ and LZ change
		TSBM Rdf..Rdl,Rsf..Rsl	;the source and destination array must
					;belong to different register banks
		TSBM Rdf..Rdl,Im5	;immediate 5-bit operand
Examples:
		TSBM R10..R11,R74..R75
		TSBM I24..I31,R88..R95
		TSBM R99..R101,I43..I45
		TSBM R64..R66,&H0F

--------------------

Mnemonic:	TXR (Test Logical XOR)
Syntax:		TXR dst,src
Execution:	dst XOR src
Description:	Logically XORs the source and the destination, but the result
		is not written anywhere. Only the status of the flags is
		changed.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Options:
		TXR Rd,Rs	;the source and destination register must
				;belong to different register banks
		TXR Rd,Im8
		TXR (IX),Rs
		TXR (IY),Rs
Examples:
		TXR R10,R70
		TXR R80,R20
		TXR I25,R99
		TXR R88,I44
		TXR R16,&H55
		TXR (IX),R110
		TXR (IY),R47

--------------------

Mnemonic:	TXRM (Test Logical XOR Multibyte)
Syntax:		TXRM dst,src
Execution:	dst XOR src
Description:	Logically XORs two register arrays, but the result is not
		written anywhere. Only the status of the flags is changed.
		Both arrays must belong to different register banks.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		TXRM R84..R87,R20..R23
		TXRM R84..R87,I20..I23
		TXRM I33..I35,R65..R67

--------------------

Mnemonic:	WAI (WAit for an Interrupt)
Syntax:		WAI
Description:	Halts the code execution until a hardware interrupt occurs.
		Upon receipt of an interrupt, the execution will be resumed at
		the instruction immediately following WAI.
		While waiting, the microprocessor will respond to:
		- any INT0..INT2 or timer event, provided that the bit 7 of
		  the IE register is set, even if the individual interrupts
		  would be disabled (cleared bits 0..3 of the IE register)
		- a pressed key event, regardless of the IE register state
Flags:		none affected
Example:
		WAI

--------------------

Mnemonic:	XC (Exchange bytes)
Syntax:		XC reg1,reg2
Execution:	reg1 <-> reg2
Description:	Exchanges the contents of two registers.
Flags:		none affected
Options:
		XC Rd,Rs	;both registers must belong to different banks
Examples:
		XC R10,R70
		XC R80,R20
		XC I25,R99
		XC R88,I44

--------------------

Mnemonic:	XCH (Exchange Higher Digit)
Syntax:		XCH dst,src
Execution:	lower digit of dst <-> upper digit of src
Description:	Exchanges the upper digit of the source register with the
		lower digit of the destination register. Both registers must
		belong to different banks.
Flags:		none affected
Examples:
		LD R10,&H34
		LD R70,&H56
		XCH R10,R70	;R10=&H35, R70=&H46

		Note: instructions XCH R10,R70 and XCL R70,R10 are equivalent

		XCH I25,R99
		XCH R88,I44

--------------------

Mnemonic:	XCHM (Exchange Higher Digits Multibyte)
Syntax:		XCHM dst,src
Execution:	lower digits of dst <-> upper digits of src
Description:	Exchanges the upper digits of the source register array with
		the lower digits of the destination register array. Both
		arrays must belong to different banks.
Flags:		none affected
Examples:
		LD R10,&H34
		LD R11,&H56
		LD R74,&HAB
		LD R75,&HCD
		XCHM R10..R11,R74..R75	;R10=&H3A, R11=&H5C
					;R74=&H4B, R75=&H6D

		Note: instructions XCHM R10..R11,R74..R75 and
		      XCLM R74..R75,R10..R11 are equivalent

		XCHM R84..R85,I20..I21
		XCHM I48..I55,R80..R87

--------------------

Mnemonic:	XCHS (Exchange Higher Digit then Swap Digits)
Syntax:		XCHS dst,src
Execution:	lower digit of dst <-> upper digit of src,
		swap digits both in dst and src
Description:	Exchanges the upper digit of the source register with the
		lower digit of the destination register, then swaps digits in
		both registers. The registers must belong to different banks.
Flags:		none affected
Examples:
		LD R80,&HAB
		LD R16,&HCD
		XCHS R80,R16
		;R80 = &HCA
		;R16 = &HDB
		;it's a rotation of four digits (nibbles) clockwise

		Note: instructions XCHS R80,R6 and XCLS R6,R80 are equivalent

		XCHS R10,R70
		XCHS I25,R99
		XCHS R88,I44

--------------------

Mnemonic:	XCHSM (Exchange Higher Digits then Swap Digits, Multibyte)
Syntax:		XCHSM dst,src
Execution:	lower digits of dst <-> upper digits of src,
		swap digits both in dst and src
Description:	Exchanges the upper digits of the source register array with
		the lower digits of the destination register array, then swaps
		digits in all registers of both arrays. The arrays must belong
		to different banks.
Flags:		none affected
Examples:
		LD R84,&H67
		LD R85,&H89
		LD R20,&HAB
		LD R21,&HCD
		XCHSM R84..R85,R20..R21	;R84=&HA6, R85=&HC8
					;R20=&HB7, R21=&HD9

		Note: instructions XCHSM R84..R85,R20..R21 and
		      XCLSM R20..R21,R84..R85 are equivalent

		XCHSM R84..R85,I20..I21
		XCHSM I48..I55,R80..R87

--------------------

Mnemonic:	XCL (Exchange Lower Digit)
Syntax:		XCL dst,src
Execution:	upper digit of dst <-> lower digit of src
Description:	Exchanges the lower digit of the source register with the
		upper digit of the destination register. Both registers must
		belong to different banks.
Flags:		none affected
Example:
		LD R10,&H34
		LD R70,&H56
		XCL R10,R70	;R10=&H64, R70=&H53

		Note: instructions XCL R10,R70 and XCH R70,R10 are equivalent

		XCL R70,R10
		XCL I25,R99
		XCL R88,I44

--------------------

Mnemonic:	XCLM (Exchange Lower Digits Multibyte)
Syntax:		XCLM dst,src
Execution:	upper digits of dst <-> lower digits of src
Description:	Exchanges the lower digits of the source register array with
		the upper digits of the destination register array. Both
		arrays must belong to different banks.
Flags:		none affected
Example:
		LD R30,&H34
		LD R31,&H56
		LD R78,&HAB
		LD R79,&HCD
		XCLM R78..R79,R30..R31	;R30=&H3A, R31=&H5C
					;R78=&H4B, R79=&H6D

		Note: instructions XCLM R78..R79,R30..R31 and
		      XCHM R30..R31,R78..R79 are equivalent

		XCLM R96..R97,I24..I25
		XCLM I3..I6,R83..R86

--------------------

Mnemonic:	XCLS (Exchange Lower Digit then Swap Digits)
Syntax:		XCLS dst,src
Execution:	upper digit of dst <-> lower digit of src,
		swap digits both in dst and src
Description:	Exchanges the lower digit of the source register with the
		upper digit of the destination register, then swaps digits in
		both registers. The registers must belong to different banks.
Flags:		none affected
Examples:
		LD R80,&HAB
		LD R20,&HCD
		XCLS R80,R20
		;R80 = &HBD
		;R20 = &HAC
		;it's a rotation of four digits (nibbles) counterclockwise

		Note: instructions XCLS R80,R20 and XCHS R20,R80 are
		      equivalent

		XCLS R10,R70
		XCLS I25,R99
		XCLS R88,I44

--------------------

Mnemonic:	XCLSM (Exchange Lower Digits then Swap Digits, Multibyte)
Syntax:		XCLSM dst,src
Execution:	upper digits of dst <-> lower digits of src,
		swap digits both in dst and src
Description:	Exchanges the lower digits of the source register array with
		the upper digits of the destination register array, then swaps
		digits in all registers of both arrays. The arrays must belong
		to different banks.
Flags:		none affected
Examples:
		LD R80,&H34
		LD R81,&H56
		LD R24,&HAB
		LD R25,&HCD
		XCLSM R80..R81,R24..R25	;R80=&H4B, R81=&H6D
					;R24=&H3A, R25=&H5C

		Note: instructions XCLSM R80..R81,R24..R25 and
		      XCHSM R24..R25,R80..R81 are equivalent

		XCLSM R96..R97,I24..I25
		XCLSM I3..I6,R83..R86

--------------------

Mnemonic:	XCM (Exchange Multibyte)
Syntax:		XCM dst,src
Execution:	register array 1 <-> register array 2
Description:	Exchanges the contents of two register arrays. Both arrays
		must belong to different register banks.
Flags:		none affected
Examples:
		XCM R10..R13,R74..R77	;R10 <-> R74
					;R11 <-> R75
					;R12 <-> R76
					;R13 <-> R77

		XCM I10..I13,R82..R85
		XCM R64..R66,I56..I58

--------------------

Mnemonic:	XCS (Exchange bytes then Swap digits in each byte)
Syntax:		XCS reg1,reg2
Execution:	reg1 <-> reg2, swap digits in reg1, swap digits in reg2
Description:	Exchanges the contents of two registers, then swaps digits in
		both of them. The registers must belong to different banks.
Flags:		none affected
Examples:
		XCS R10,R70
		XCS R80,R20
		XCS I25,R99
		XCS R88,I44

--------------------

Mnemonic:	XCSM (Exchange then Swap digits in each byte, Multibyte)
Syntax:		XCSM array1,array2
Execution:	array1 <-> array2, swap digits in each byte of array1, swap
		digits in each byte of array2
Description:	Exchanges the contents of two register arrays, then swaps
		digits in each byte of both arrays. The arrays must belong to
		different register banks.
Flags:		none affected
Examples:
		XCSM R80..R85,R24..R29
		XCSM I10..I13,R82..R85
		XCSM R64..R66,I56..I58

--------------------

Mnemonic:	XR (Logical XOR)
Syntax:		XR dst,src
Execution:	dst <- dst XOR src
Description:	Logically XORs the source and the destination and stores the
		result in the destination.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Options:
		XR Rd,Rs	;the source and destination register must
				;belong to different register banks
		XR Rd,Im8
		XR (IX),Rs
		XR (IY),Rs
		XR (IX),Im8
		XR (IY),Im8
Examples:
		XR R10,R70
		XR R80,R20
		XR I25,R99
		XR R88,I44
		XR R16,&H55
		XR (IX),R110
		XR (IY),R47
		XR (IX),&HFE
		XR (IY),&H6A

--------------------

Mnemonic:	XRM (Logical XOR Multibyte)
Syntax:		XRM dst,src
Execution:	dst <- dst XOR src
Description:	Logically XORs the source and the destination array and stores
		the result in the destination array. Both arrays must belong
		to different register banks.
Flags:		C=0, H=0, V=0, Z, UZ and LZ change
Examples:
		XRM R84..R87,R20..R23
		XRM R100..R103,I20..I23
		XRM I8..I15,R72..R79

--------------------

