Instruction encoding for following Casio microprocessors:
NM-325 / uPD1037 / HD62023
NM-326 / uPD3055 / HD62076

All numbers are hexadecimal unless stated otherwise.
Most additional mnemonic names were adopted from the Casio's HD61700 official
instruction set.



Opcode vs Instruction Cross Reference
=====================================

opcode	#bytes	#cycles		addr. mode	mnemonic
------	------	slow	fast	----------	--------

00	3	13	10	Reg1,Reg6	TNA/NA Rd,Rs
01	3	13	10	Reg1,Reg6	TXR/XR Rd,Rs
02	3	13	10	Reg1,Reg6	TSBB/SBB Rd,Rs
03	3	13	10	Reg1,Reg6	TSB/SB Rd,Rs
04	3	13	10	Reg1,Reg6	TAN/AN Rd,Rs
05	3	13	10	Reg1,Reg6	TOR/OR Rd,Rs
06	3	13	10	Reg1,Reg6	TADB/ADB Rd,Rs
07	3	13	10	Reg1,Reg6	TAD/AD Rd,Rs

08	3	13	10	Reg3,Im8	TNA/NA Rd,nn
09	3	13	10	Reg3,Im8	TXR/XR Rd,nn
0A	3	13	10	Reg3,Im8	TSBB/SBB Rd,nn
0B	3	13	10	Reg3,Im8	TSB/SB Rd,nn
0C	3	13	10	Reg3,Im8	TAN/AN Rd,nn
0D	3	13	10	Reg3,Im8	TOR/OR Rd,nn
0E	3	13	10	Reg3,Im8	TADB/ADB Rd,nn
0F	3	13	10	Reg3,Im8	TAD/AD Rd,nn

10	3	9+4*i	6+4*i	Reg1,Reg9	TNAM/NAM Rdf..Rdl,Rsf..Rsl
11	3	9+4*i	6+4*i	Reg1,Reg9	TXRM/XRM Rdf..Rdl,Rsf..Rsl
12	3	9+4*i	6+4*i	Reg1,Reg9	TSBBM/SBBM Rdf..Rdl,Rsf..Rsl
13	3	9+4*i	6+4*i	Reg1,Reg9	TSBM/SBM Rdf..Rdl,Rsf..Rsl
14	3	9+4*i	6+4*i	Reg1,Reg9	TANM/ANM Rdf..Rdl,Rsf..Rsl
15	3	9+4*i	6+4*i	Reg1,Reg9	TORM/ORM Rdf..Rdl,Rsf..Rsl
16	3	9+4*i	6+4*i	Reg1,Reg9	TADBM/ADBM Rdf..Rdl,Rsf..Rsl
17	3	9+4*i	6+4*i	Reg1,Reg9	TADM/ADM Rdf..Rdl,Rsf..Rsl

18 00	3	13	10	Reg4,Reg6	PLA 16-bit-reg. or PLA Rd,Rs
18 80	3	15	12	Reg4,Reg6	IJMP 16-bit-reg. or IJMP Rd,Rs

19 00	3	13	10	Reg1,Reg6	BIT Rd,Rs ;NOT Rd AND Rs
19 80	3	13	10	Reg5,Im8	BIT Rd,nn ;NOT Rd AND nn

1A	3	9+4*i	6+4*i	Reg3,Reg8Im5	TSBBM/SBBM Rf..Rl,nn
1B	3	9+4*i	6+4*i	Reg3,Reg8Im5	TSBM/SBM Rf..Rl,nn

; search memory for data in Rs (in the bank 0),
; Rd (in the bank 1) used as counter, decremented to 0
1C 00	3	22+13*i	16+12*i	Reg5,Reg6	SDN Rd,Rs ;comp. -(IX) with Rs
1C 80	3	22+13*i	16+12*i	Reg5,Reg6	SUP Rd,Rs ;comp. +(IX) with Rs

; similar function as 1C but stops after the first comparison
1D 00	3	22+13*i	16+12*i	Reg5,Reg6	???
1D 80	3	22+13*i	16+12*i	Reg5,Reg6	???

1E	3	9+4*i	6+4*i	Reg3,Reg8Im5	TADBM/ADBM Rf..Rl,nn
1F	3	9+4*i	6+4*i	Reg3,Reg8Im5	TADM/ADM Rf..Rl,nn

20 00	3	13	10	Reg5,Im8	LD Rd,Rd,nn ;in both banks
20 80	3	13	10	Reg5,Im8	LD Rd,nn

; exchange/load bytes
21 00	3	13	10	Reg1,Reg6	XC Rd,Rs
21 80	3	13	10	Reg1,Reg6	LD Rd,Rs

22	3	13	10	Reg1,Reg6	TSBBC/SBBC Rd,Rs
23	3	13	10	Reg1,Reg6	TSBC/SBC Rd,Rs

; swap digits
24 00	3	13	10	Reg1,Reg6	SWP Rd,Rs ;in two registers
24 80	3	13	10	Reg1,Reg6	SWP Rd ;in a single register

; exchange/load bytes then swap digits
25 00	3	13	10	Reg1,Reg6	XCS Rd,Rs
25 80	3	13	10	Reg1,Reg6	LDS Rd,Rs

26	3	13	10	Reg1,Reg6	TADBC/ADBC Rd,Rs
27	3	13	10	Reg1,Reg6	TADC/ADC Rd,Rs

; exchange/load digit
28 00	3	13	10	Reg1,Reg6	XCH/XCL Rd,Rs
28 80	3	13	10	Reg1,Reg6	LDH/LDL Rd,Rs

; exchange/load digit then swap digits
29 00	3	13	10	Reg1,Reg6	XCHS/XCLS Rd,Rs
29 80	3	13	10	Reg1,Reg6	LDHS/LDLS Rd,Rs

2A	3	13	10	Reg3,Im8	TSBBC/SBBC Rd,nn
2B	3	13	10	Reg3,Im8	TSBC/SBC Rd,nn

; exchange/load digit then swap digits
2C 00	3	13	10	Reg1,Reg6	XCHS/XCLS Rd,Rs
2C 80	3	13	10	Reg1,Reg6	LDHS/LDLS Rd,Rs

; exchange/load digit
2D 00	3	13	10	Reg1,Reg6	XCH/XCL Rd,Rs
2D 80	3	13	10	Reg1,Reg6	LDH/LDL Rd,Rs

2E	3	13	10	Reg3,Im8	TADBC/ADBC Rd,nn
2F	3	13	10	Reg3,Im8	TADC/ADC Rd,nn

; loads 5-bit immediate data to all specified registers
30 00	3	9+4*i	6+4*i	Reg5,Reg8Im5	LDM Rf..Rl,Rf..Rl,nn
30 80	3	9+4*i	6+4*i	Reg5,Reg8Im5	LDM Rf..Rl,nn

31 00	3	9+4*i	6+4*i	Reg1,Reg9	XCM Rdf..Rdl,Rsf..Rsl
31 80	3	9+4*i	6+4*i	Reg1,Reg9	LDM Rdf..Rdl,Rsf..Rsl

32	3	9+4*i	6+4*i	Reg1,Reg9	TSBBCM/SBBCM Rdf..Rdl,Rsf..Rsl
33	3	9+4*i	6+4*i	Reg1,Reg9	TSBCM/SBCM Rdf..Rdl,Rsf..Rsl

; swap digits
34 00	3	9+4*i	6+4*i	Reg1,Reg9	SWPM Rdf..Rdl,Rsf..Rsl
34 80	3	9+4*i	6+4*i	Reg1,Reg9	SWPM Rdf..Rdl

; exchange/load register arrays then swap digits
35 00	3	9+4*i	6+4*i	Reg1,Reg9	XCSM Rdf..Rdl,Rsf..Rsl
35 80	3	9+4*i	6+4*i	Reg1,Reg9	LDSM Rdf..Rdl,Rsf..Rsl

36	3	9+4*i	6+4*i	Reg1,Reg9	TADBCM/ADBCM Rdf..Rdl,Rsf..Rsl
37	3	9+4*i	6+4*i	Reg1,Reg9	TADCM/ADCM Rdf..Rdl,Rsf..Rsl

; exchange/load digit, multibyte
38 00	3	9+4*i	6+4*i	Reg1,Reg9	XCHM/XCLM Rdf..Rdl,Rsf..Rsl
38 80	3	9+4*i	6+4*i	Reg1,Reg9	LDHM/LDLM Rdf..Rdl,Rsf..Rsl

; exchange/load digit then swap digits, multibyte
39 00	3	9+4*i	6+4*i	Reg1,Reg9	XCHSM/XCLSM Rdf..Rdl,Rsf..Rsl
39 80	3	9+4*i	6+4*i	Reg1,Reg9	LDHSM/LDLSM Rdf..Rdl,Rsf..Rsl

3A	3	9+4*i	6+4*i	Reg3,Reg8Im5	TSBBCM/SBBCM Rf..Rl,nn
3B	3	9+4*i	6+4*i	Reg3,Reg8Im5	TSBCM/SBCM Rf..Rl,nn

; exchange/load digit then swap digits, multibyte
3C 00	3	9+4*i	6+4*i	Reg1,Reg9	XCHSM/XCLSM Rdf..Rdl,Rsf..Rsl
3C 80	3	9+4*i	6+4*i	Reg1,Reg9	LDHSM/LDLSM Rdf..Rdl,Rsf..Rsl

; exchange/load digit, multibyte
3D 00	3	9+4*i	6+4*i	Reg1,Reg9	XCHM/XCLM Rdf..Rdl,Rsf..Rsl
3D 80	3	9+4*i	6+4*i	Reg1,Reg9	LDHM/LDLM Rdf..Rdl,Rsf..Rsl

3E	3	9+4*i	6+4*i	Reg3,Reg8Im5	TADBCM/ADBCM Rf..Rl,nn
3F	3	9+4*i	6+4*i	Reg3,Reg8Im5	TADCM/ADCM Rf..Rl,nn

40	2	13/16	10/12	Reg7		TNA/NA (IX),Rs
41	2	13/16	10/12	Reg7		TXR/XR (IX),Rs
42	2	13/16	10/12	Reg7		TSBB/SBB (IX),Rs
43	2	13/16	10/12	Reg7		TSB/SB (IX),Rs
44	2	13/16	10/12	Reg7		TAN/AN (IX),Rs
45	2	13/16	10/12	Reg7		TOR/OR (IX),Rs
46	2	13/16	10/12	Reg7		TADB/ADB (IX),Rs
47	2	13/16	10/12	Reg7		TAD/AD (IX),Rs

48	2	16	12	Im8		NA (IX),nn
49	2	16	12	Im8		XR (IX),nn
4A	2	16	12	Im8		SBB (IX),nn
4B	2	16	12	Im8		SB (IX),nn
4C	2	16	12	Im8		AN (IX),nn
4D	2	16	12	Im8		OR (IX),nn
4E	2	16	12	Im8		ADB (IX),nn
4F	2	16	12	Im8		AD (IX),nn

50	2	13/16	10/12	Reg7		TNA/NA (IY),Rs
51	2	13/16	10/12	Reg7		TXR/XR (IY),Rs
52	2	13/16	10/12	Reg7		TSBB/SBB (IY),Rs
53	2	13/16	10/12	Reg7		TSB/SB (IY),Rs
54	2	13/16	10/12	Reg7		TAN/AN (IY),Rs
55	2	13/16	10/12	Reg7		TOR/OR (IY),Rs
56	2	13/16	10/12	Reg7		TADB/ADB (IY),Rs
57	2	13/16	10/12	Reg7		TAD/AD (IY),Rs

58	2	16	12	Im8		NA (IY),nn
59	2	16	12	Im8		XR (IY),nn
5A	2	16	12	Im8		SBB (IY),nn
5B	2	16	12	Im8		SB (IY),nn
5C	2	16	12	Im8		AN (IY),nn
5D	2	16	12	Im8		OR (IY),nn
5E	2	16	12	Im8		ADB (IY),nn
5F	2	16	12	Im8		AD (IY),nn

60 00	2	10	8	Reg5		ROD Rd
60 80	2	10	8	Reg5		ROU Rd

61 00	2	10	8	Reg5		DID Rd
61 80	2	10	8	Reg5		DIU Rd

62	2	10	8	Reg3		TCMPB/CMPB Rd
63	2	10	8	Reg3		TCMP/CMP Rd

64 00	2	10	8	Reg5		BYD Rd
64 80	2	10	8	Reg5		BYU Rd

; single byte equivalents of BNDM/BNUM, do nothing
65 00	2	10	8	Reg5		BND Rd
65 80	2	10	8	Reg5		BNU Rd

66	2	10	8	Reg3		TMTB/MTB Rd ;mul. by 2, BCD
67	2	10	8	Reg3		TBIU/BIU Rd

68 00	2	17	14	Reg5		ST -(IX),Rs
68 80	2	15	12	Reg5		LD Rd,(IX)-

69 00	2	17	14	Reg5		ST -(IY),Rs
69 80	2	15	12	Reg5		LD Rd,(IY)-
	
6A 00	2	17	14	Reg5		ST -(IZ),Rs
6A 80	2	15	12	Reg5		LD Rd,(IZ)-

6B 00	2	17	14	Reg5		ST -(SP),Rs or PUSH Rs
6B 80	2	15	12	Reg5		LD Rd,(SP)-

6C 00	2	17	14	Reg5		ST +(IX),Rs
6C 80	2	15	12	Reg5		LD Rd,(IX)+

6D 00	2	17	14	Reg5		ST +(IY),Rs
6D 80	2	15	12	Reg5		LD Rd,(IY)+

6E 00	2	17	14	Reg5		ST +(IZ),Rs
6E 80	2	15	12	Reg5		LD Rd,(IZ)+

6F 00	2	17	14	Reg5		ST +(SP),Rs
6F 80	2	15	12	Reg5		LD Rd,(SP)+ or POP Rd

70 00	3	9+4*i	6+4*i	Reg1,Reg9	RODM Rf..Rl
70 80	3	9+4*i	6+4*i	Reg1,Reg9	ROUM Rf..Rl

71 00	3	9+4*i	6+4*i	Reg1,Reg9	DIDM Rf..Rl
71 80	3	9+4*i	6+4*i	Reg1,Reg9	DIUM Rf..Rl

72	3	9+4*i	6+4*i	Reg1,Reg9	TCMPBM/CMPBM Rf..Rl
73	3	9+4*i	6+4*i	Reg1,Reg9	TCMPM/CMPM Rf..Rl

74 00	3	9+4*i	6+4*i	Reg1,Reg9	BYDM Rf..Rl
74 80	3	9+4*i	6+4*i	Reg1,Reg9	BYUM Rf..Rl

; as BYDM/BYUM but the last register not cleared
75 00	3	9+4*i	10+4*i	Reg1,Reg9	BNDM Rf..Rl
75 80	3	9+4*i	10+4*i	Reg1,Reg9	BNUM Rf..Rl

76	3	9+4*i	10+4*i	Reg1,Reg9	TMTBM/MTBM Rf..Rl ;multiply by 2, BCD
77	3	9+4*i	10+4*i	Reg1,Reg9	TBIUM/BIUM Rf..Rl

78 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM -(IX),Rf..Rl
78 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IX)-

79 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM -(IY),Rf..Rl
79 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IY)-

7A 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM -(IZ),Rf..Rl
7A 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IZ)-

7B 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM -(SP),Rf..Rl
7B 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(SP)-

7C 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM +(IX),Rf..Rl
7C 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IX)+

7D 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM +(IY),Rf..Rl
7D 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IY)+

7E 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM +(IZ),Rf..Rl
7E 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(IZ)+

7F 00	3	13+5*i	10+4*i	Reg1,Reg9	STM/STLM +(SP),Rf..Rl
7F 80	3	13+5*i	10+4*i	Reg1,Reg9	LDM Rf..Rl,(SP)+

80 00	3	20	16	Reg5,Offs8	ST (IX-nn),Rs
80 80	3	20	16	Reg5,Offs8	LD Rd,(IX-nn)

81 00	3	20	16	Reg5,Offs8	ST (IY-nn),Rs
81 80	3	20	16	Reg5,Offs8	LD Rd,(IY-nn)

82 00	3	20	16	Reg5,Offs8	ST (IZ-nn),Rs
82 80	3	20	16	Reg5,Offs8	LD Rd,(IZ-nn)

83 00	3	20	16	Reg5,Offs8	ST (SP-nn),Rs
83 80	3	20	16	Reg5,Offs8	LD Rd,(SP-nn)

84 00	3	20	16	Reg5,Offs8	ST (IX+nn),Rs
84 80	3	20	16	Reg5,Offs8	LD Rd,(IX+nn)

85 00	3	20	16	Reg5,Offs8	ST (IY+nn),Rs
85 80	3	20	16	Reg5,Offs8	LD Rd,(IY+nn)

86 00	3	20	16	Reg5,Offs8	ST (IZ+nn),Rs
86 80	3	20	16	Reg5,Offs8	LD Rd,(IZ+nn)

87 00	3	20	16	Reg5,Offs8	ST (SP+nn),Rs
87 80	3	20	16	Reg5,Offs8	LD Rd,(SP+nn)

; transfer of immediate data to the status registers
88	2	10	8	Im8		PST IE,nn ;Interrupt Enable
89	2	10	8	Im8		PST DS,nn ;Data Segment
8A	2	10	8	Im8		PST KY,nn ;Keyboard Port
8B	2	10	8	Im8		PST PD,nn ;8-bit port

8C 00	2	10	8	Im7		PST S4,nn
8C 80	2	10	8	Im7		PST S8,nn
8D 00	2	10	8	Im7		PST S5,nn ;disp. clock divisor
8D 80	2	10	8	Im7		PST AS,nn ;Address Select
8E 00	2	10	8	Im7		PST S6,nn ;disp. height & control
8E 80	2	10	8	Im7		PST TM,nn ;timer divisor
8F 00	2	10	8	Im7		PST S7,nn ;display width
8F 80	2	10	8	Im7		PST PE,nn ;4-bit port

90 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IX-nn),Rf..Rl
90 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IX-nn)

91 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IY-nn),Rf..Rl
91 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IY-nn)

92 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IZ-nn),Rf..Rl
92 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IZ-nn)

93 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (SP-nn),Rf..Rl
93 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(SP-nn)

94 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IX+nn),Rf..Rl
94 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IX+nn)

95 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IY+nn),Rf..Rl
95 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IY+nn)

96 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (IZ+nn),Rf..Rl
96 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(IZ+nn)

97 00	3	15+5*i	12+4*i	Reg5,Reg8Of5	STM (SP+nn),Rf..Rl
97 80	3	15+5*i	12+4*i	Reg5,Reg8Of5	LDM Rf..Rl,(SP+nn)

; transfers between a data register and a status register
98 00	2	10	8	Reg5		PST IE,Rs ;Interrupt Enable
98 80	2	10	8	Reg5		GST Rd,IE

99 00	2	10	8	Reg5		PST DS,Rs ;Data Segment
99 80	2	10	8	Reg5		GST Rd,DS

9A 00	2	10	8	Reg5		PST KY,Rs ;8-bit Keyboard Port
9A 80	2	10	8	Reg5		GST Rd,KY

9B 00	2	10	8	Reg5		PST PD,Rs ;8-bit port
9B 80	2	10	8	Reg5		GST Rd,PD

9C 00	2	10	8	Reg5		PST F,Rs ;Flags
9C 80	2	10	8	Reg5		GST Rd,F

9D 00	2	10	8	Reg5		PST AS,Rs ;Address Select
9D 80	2	10	8	Reg5		GST Rd,AS

; block transfer, Rd used as counter, decremented to 0
9E 00	2	16+14*i	12+12*i	Reg5		BDN Rd
9E 80	2	16+14*i	12+12*i	Reg5		BUP Rd

; the opcode 9F seems to have the same function as 9E
9F 00	2	16+14*i	14+12*i	Reg5
9F 80	2	16+14*i	14+12*i	Reg5

A0..AE	3	13	10	Im16		JMP cc,addr

AF	1	-	-	-		OFF ;stops the system

B0..BE	3	13/19	10/14	Im16		CAL cc,addr

BF	1	-	-	-		WAI

C0..CE	1	7/15	6/12	-		RTN cc

CF	1	15	12	-		RTI

D0	3	13	10	Im16		LDW IX,nnnn
D1	3	13	10	Im16		LDW IY,nnnn
D2	3	13	10	Im16		LDW IZ,nnnn
D3	3	13	10	Im16		LDW V3,nnnn
D4	3	13	10	Im16		LDW V2,nnnn
D5	3	13	10	Im16		LDW V1,nnnn
D6	3	13	10	Im16		LDW V0,nnnn
D7	3	13	10	Im16		LDW SP,nnnn

D8	2	12/14	10/12	Im7Reg		SBW IX,nn / SBW IX,Rs
D9	2	12/14	10/12	Im7Reg		SBW IY,nn / SBW IY,Rs
DA	2	12/14	10/12	Im7Reg		SBW IZ,nn / SBW IZ,Rs
DB	2	12/14	10/12	Im7Reg		SBW SP,nn / SBW SP,Rs
DC	2	12/14	10/12	Im7Reg		ADW IX,nn / ADW IX,Rs
DD	2	12/14	10/12	Im7Reg		ADW IY,nn / ADW IY,Rs
DE	2	12/14	10/12	Im7Reg		ADW IZ,nn / ADW IZ,Rs
DF	2	12/14	10/12	Im7Reg		ADW SP,nn / ADW SP,Rs

E0..EE	2	10	8	Im8		SJMP cc,addr

EF	1	7	6	-		NOP

F0..FE	2	10/16	8/12	Im8		SCAL cc,addr

FF	1	15	12	-		TRP



Number of cycles
================

For the clock frequency of 2MHz the period of a cycle is 0.5us.

The values are decimal, not hex.

The values apply for code stored in external memory.
Column 'slow' - a memory access requiring 3 clock cycles
Column 'fast' - a memory access requiring 2 clock cycles

Execution time from the microprocessor's internal ROM is shorter than in the
'fast' mode by #opcode_bytes * 2 clock cycles, because accessing the internal
ROM doesn't consume any clock cycles.
In case of instructions SUP, SDN, BUP and BDN the opcode bytes are fetched
twice which results in following number of cycles in the internal ROM:
SUP, SDN: 4+12*i
BUP, BDN: 4+12*i

i = size of the register array(s) or number of processed bytes

Two values are specified in following cases:
	result of operation not stored / result stored
	call or return not taken / call or return taken
	ADW/SBW immediate operand / register operand



Operands
========

Reg1 = data register in range 40..7F

bits: FSRRRRRR

F = function:	1: result of operation stored in the destination register
		0: check mode, result not stored, only flags affected

S = swap:	1: the result of an operation between the contents of the
		   register specified in the 2nd byte and the contents of
		   the register specified in the 3rd byte is stored in the
		   register specified in the 2nd byte
		0: the result of an operation between the contents of the
		   register specified in the 3rd byte and the contents of
		   the register specified in the 2nd byte is stored in the
		   register specified in the 3rd byte (reversed operands)

R = register, order of bits: **543210
    In case of unary multi byte operations (for example BIUM) bits 543 (page
    specification) are ignored when swap bit S=0.

-----------------------------------------------------------------------------

Reg3 = data register in range 00..7F

bits: FRRRRRRR

F = function:	1: result of operation stored in the destination register
		0: check mode, result not stored, only flags affected

R = register, order of bits: *6543210

-----------------------------------------------------------------------------

Reg4 = high-order data register of a 16-bit register

bits: OxRRRRRR

O = operation, extension of the first opcode byte

x = should be cleared with 0

R = register, order of bits: **543210

-----------------------------------------------------------------------------

Reg5 = data register in range 00..7F

bits: ORRRRRRR

O = operation, extension of the first opcode byte

R = register, order of bits: *6543210

-----------------------------------------------------------------------------

Reg6 = data register in range 00..3F

bits: RRRKxRRR

R = register, order of bits: 210**543

K = 0: direct specification
    1: indirect specification with the contents of the AS register

x = should be cleared with 0

-----------------------------------------------------------------------------

Reg7 = data register in range 00..7F

bits: FRRRRRRR

F = function:	1: result of operation stored in the destination memory
		0: check mode, result not stored, only flags affected

R = register, order of bits: *6543210  NOTE: bit 6 is inverted!!!

-----------------------------------------------------------------------------

Reg8Im5 = second argument of multibyte operations

bits: RRRIIIII

L = last register of the register array, order of bits: 210*****

I = immediate data, order of bits: ***43210

-----------------------------------------------------------------------------

Reg8Of5 = second argument of multibyte operations

bits: RRRIIIII

R = last register of the register array, order of bits: 210*****

I = immediate 5-bit offset, order of bits: ***43210

For the STM instructions add 1 to the encoded 5-bit offset to get actual
offset value.

-----------------------------------------------------------------------------

Reg9 = second argument of multibyte operations

bits: LLLKFRRR

L = last register of the register array, order of bits: 210*****

K = 0: direct specification
    1: indirect specification with the contents of the AS register

F = function	0: data stored in the memory
		1: data stored in the memory and transferred to the LCD driver
Bit F is set for the STLM instruction and cleared for other ones.

R = page of the register array in the bank 0, order of bits: *****543
    In case of a single register array (for example BIUM, STM) ignored when
    swap bit S=1.

-----------------------------------------------------------------------------

Im7Reg = immediate 7-bit value or a data register

0IIIIIII - immediate 7-bit value, order of bits: *6543210

1RRRRRRR - data register, order of bits: *6543210

-----------------------------------------------------------------------------

Im7 = immediate 7-bit value

-----------------------------------------------------------------------------

Im8 = immediate 8-bit value

-----------------------------------------------------------------------------

Im16 = immediate 16-bit value, the most significant byte first

-----------------------------------------------------------------------------

Offs8 = immediate 8-bit offset

For the ST instructions add 1 to the operand byte to get actual affset.

-----------------------------------------------------------------------------

cc = Conditional Code

bits of the opcode: OOOOCCCC

O = operation code

C = conditional code, order of bits: ****3210
	0 = Key Not Pressed
	1 = Not Lower Zero
	2 = Not Upper Zero
	3 = Not Zero
	4 = No Overflow
	5 = Not Half Carry
	6 = Not Carry
	7 = unconditional jump/call/return
	8 = Key Pressed
	9 = Lower Zero
	A = Upper Zero
	B = Zero
	C = Overflow
	D = Half Carry
	E = Carry



Appendix 1 - examples of opcodes 28, 29, 2C, 2D
===============================================

28,1B,C1 - lower digit of R&H5B <-> upper digit of R&H0E
28,5B,C1 - lower digit of R&H5B <-> upper digit of R&H0E
28,9B,C1 - lower digit of R&H5B --> upper digit of R&H0E
28,DB,C1 - lower digit of R&H5B <-- upper digit of R&H0E

29,1B,C1 - upper digit of R&H5B <-> lower digit of R&H0E, then swap digits
 in both registers
29,5B,C1 - upper digit of R&H5B <-> lower digit of R&H0E, then swap digits
 in both registers
29,9B,C1 - upper digit of R&H5B --> lower digit of R&H0E, then swap digits
 in R&H0E
29,DB,C1 - upper digit of R&H5B <-- lower digit of R&H0E, then swap digits
 in R&H5B

2C,1B,C1 - lower digit of R&H5B <-> upper digit of R&H0E, then swap digits
 in both registers
2C,5B,C1 - lower digit of R&H5B <-> upper digit of R&H0E, then swap digits
 in both registers
2C,9B,C1 - lower digit of R&H5B --> upper digit of R&H0E, then swap digits
 in R&H0E
2C,DB,C1 - lower digit of R&H5B <-- upper digit of R&H0E, then swap digits
 in R&H5B

2D,1B,C1 - upper digit of R&H5B <-> lower digit of R&H0E
2D,5B,C1 - upper digit of R&H5B <-> lower digit of R&H0E
2D,9B,C1 - upper digit of R&H5B --> lower digit of R&H0E
2D,DB,C1 - upper digit of R&H5B <-- lower digit of R&H0E



Appendix 2 - examples of opcodes 28, 29, 2C, 2D
===============================================

38,1B,C1 - lower digits of R&H5B..R&H5E <-> upper digits of R&H0B..R&H0E
38,5B,C1 - lower digits of R&H5B..R&H5E <-> upper digits of R&H0B..R&H0E
38,9B,C1 - lower digits of R&H5B..R&H5E --> upper digits of R&H0B..R&H0E
38,DB,C1 - lower digits of R&H5B..R&H5E <-- upper digits of R&H0B..R&H0E

39,1B,C1 - upper digits of R&H5B..R&H5E <-> lower digits of R&H0B..R&H0E, then
 swap digits in all registers of both arrays
39,5B,C1 - upper digits of R&H5B..R&H5E <-> lower digits of R&H0B..R&H0E, then
 swap digits in all registers of both arrays
39,9B,C1 - upper digits of R&H5B..R&H5E --> lower digits of R&H0B..R&H0E, then
 swap digits in R&H0B..R&H0E
39,DB,C1 - upper digits of R&H5B..R&H5E <-- lower digits of R&H0B..R&H0E, then
 swap digits in R&H5B..R&H5E

3C,1B,C1 - lower digits of R&H5B..R&H5E <-> upper digits of R&H0B..R&H0E, then
 swap digits in all registers of both arrays
3C,5B,C1 - lower digits of R&H5B..R&H5E <-> upper digits of R&H0B..R&H0E, then
 swap digits in all registers of both arrays
3C,9B,C1 - lower digits of R&H5B..R&H5E --> upper digits of R&H0B..R&H0E, then
 swap digits in R&H0B..R&H0E
3C,DB,C1 - lower digits of R&H5B..R&H5E <-- upper digits of R&H0B..R&H0E, then
 swap digits in R&H5B..R&H5E

3D,1B,C1 - upper digits of R&H5B..R&H5E <-> lower digits of R&H0B..R&H0E
3D,5B,C1 - upper digits of R&H5B..R&H5E <-> lower digits of R&H0B..R&H0E
3D,9B,C1 - upper digits of R&H5B..R&H5E --> lower digits of R&H0B..R&H0E
3D,DB,C1 - upper digits of R&H5B..R&H5E <-- lower digits of R&H0B..R&H0E
